29F0408RPFB MAXWELL [Maxwell Technologies], 29F0408RPFB Datasheet - Page 2

• Manufacturer Part Number: 29F0408RPFB
• Description: 32 Megabit (4M x 8-Bit) Flash Memory
• Manufacturer: MAXWELL [Maxwell Technologies]

32 Megabit (4M x 8-Bit) Flash Memory
6-17, 28-39
18-21,
24-27
1, 22
P
43
42
40
41
44
23
2
3
4
5
IN
Address Latch Enable
I/O Port: I/O0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during read
Spare Area Enable
Write Enable (WE)
Write Protect (WP)
Read Enable (RE)
Chip Enable (CE)
Read/Busy (R/B)
Command Latch
Enable (CLE)
S
(ALE)
V
(SE)
YMBOL
V
NC
V
CC
CC
SS
Q
Not Connected
The CLE input controls the path activation for commands sent to the command register.
When active high, commands are latched into the command register through the I/O ports
on the rising edge of the WE signal.
The ALE input controls the path activation for address and input data to the internal
address/data register. Addresses are latched on the rising edge or WE with ALE high, and
input data is latched when ALE is low.
The CE input is the device selection control. When CE goes high during a read operation,
the device is returned to standby mode. However, when the device is in the busy state dur-
ing program or erase, CE high is ignored, and does not return the device to standby mode.
The WE input controls writes to the I/O port. Commands, address and data are latched on
the rising edge of the WE pulse.
The RE inputs is the serial data-out control, and when active drives the data onto the I/O
bus. Data is valid t
address counter by one.
The SE input controls the spare area selection when SE is high, the device is deselected
the spare area during Read1, Sequential data input and page Program.
operations. The I/O pins float to High-Z when the chip is deselected or when the outputs are
disabled.
The WP pin provides inadvertent write/erase protection during power transitions. The inter-
nal high voltage generator is reset when the WP pin is active low.
The R/B output indicates the status of the device operation. When low, it indicates that a
program, erase or random read operation is in process and returns to high state upon com-
pletion. It is an open drain output and does not float to High-Z condition when the chip is
deselected or when outputs are disabled.
Ground
Supply Voltage
Output Buffer Voltage
T
ABLE
1. P
REA
11.08.02 Rev 2
INOUT
after the falling edge of RE which also increments the internal column
D
ESCRIPTION
D
All data sheets are subject to change without notice
ESCRIPTION
©2002 Maxwell Technologies
29F0408
All rights reserved.
2