AD28msp01KST AD [Analog Devices], AD28msp01KST Datasheet - Page 2

• Manufacturer Part Number: AD28msp01KST
• Description: PSTN Signal Port
• Manufacturer: AD [Analog Devices]

AD28msp01
Name
Analog Interface
V
V
V
V
Serial Interface
SCLK
SDI
SDO
SDIFS
IN
FB
OUTP
OUTN
V
V
OUT+
OUT–
V
V
FB
IN
Type Description
I
O
O
O
O/Z
I
O/Z
I
OUTPUT
INPUT
DIFF.
500k
AMP
Analog input to the inverting terminal of the
input amplifier.
Feedback terminal of the input amplifier.
Analog output from the noninverting terminal
of the output differential amplifier.
Analog output from inverting terminal of the
output differential amplifier.
Serial clock used for clocking data or control
bits to/from the serial port (SPORT). The
frequency of this clock is 1.7280 MHz. This
pin is 3-stated when the CS is low.
Serial data input of the SPORT. Both data
and control information are input on this pin.
This pin is ignored when CS is low.
Serial data output of the SPORT. Both data
and control information are output on this
pin. This pin is 3-stated when CS is low.
Framing synchronization signal for serial data
transfers to the AD28msp01 (via the SDI
pin). This pin is ignored when CS is low.
AMP
TSYNC
REFERENCE
VOLTAGE
t
CONV
SIGMA-DELTA
MODULATOR
SMOOTHING
ANALOG
ANALOG
FILTER
t
BAUD
CLOCK GENERATION
INTERNAL CLOCK
1.728 MHz
1.728 MHz
t
BIT
1
Figure 1. AD28msp01 Block Diagram
1
r
CONV
DECIMATION
SIGMA-DELTA
MODULATOR
DIGITAL
FILTER
DIGITAL
r
BAUD
PIN DESCRIPTIONS
16-BIT SIGMA-DELTA DAC
16-BIT SIGMA-DELTA ADC
28.8/32.0/38.4 kHz
r
BIT
16
1.728 MHz
16
–2–
M
CLK
Name
SDOFS
Clock Generation
TSYNC I
TBIT
TBAUD O
LOW-PASS FILTER
INTERPOLATION
ANTI-ALIASING
DIGITAL
DIGITAL
FILTER
CONTROL CIRCUITRY
RESET
SEQUENCER
AND
Type Description
O/Z
O
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
16
CS
16
Framing synchronization signal for serial data
transfers from the AD28msp01 (via the SDO
pin). This pin is 3-stated when CS is low.
Transmit synchronization clock. This signal is
used to synchronize the transmit clocks and
the converter clocks to an external terminal/
bit-rate clock. It is used in the V.32 TSYNC
and Asynchronous TSYNC modes and is
ignored in other operating modes. The
frequency of the external clock must be
programmed in Control Register 0. This pin
must be tied high or low if it is not being
used.
Transmit bit rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
Transmit baud rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
ANTI-IMAGING
HIGH-PASS
LOW-PASS
DIGITAL
DIGITAL
INTERPOLATION
FILTER
FILTER
RESAMPLING
REGISTERS
CONTROL
FILTER
7.2/8.0/9.6 kHz
7.2/8.0/9.6 kHz
16
16
SERIAL
PORT
SDIFS
SDOFS
SCLK
SDI
SDO
REV. A