K9K1208D0C Samsung semiconductor, K9K1208D0C Datasheet - Page 21

• Manufacturer Part Number: K9K1208D0C
• Description: 64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

PAGE PROGRAM
The device is programmed basically on a page basis. But it also allows multiple partial page programming of a byte or consecutive
bytes up to 264 may be programmed in a single page program cycle. The number of partial page programming operation in the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consist of a serial data loading period in which up to 264 bytes of data must be loaded into the device, and non-
volatile programming period in which the loaded data is programmed into the appropriate cell.
The sequential data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address
input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.
In order to program the bytes in the spare columns of 256 to 263, the pointer should be set to the spare area by writing the Read 2
command(50H) to the command register. The pointer remains in the spare area unless the Read 1 command(00H) is entered to
retum to the main area. The Page Program confirm command(10H) initiates the programming process. Writing 10H alone without
previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the
algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts,
the Status Register may be read RE and CE low after the Read Status command(70H) is written to it. The CPU can detect the com-
pletion of program cycle by monitoring the R/B output, or the Status bit(I/O
and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O
be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The com-
mand register remains in Read Status command mode until another valid command is written to the command register.
K9F8008W0M-TCB0, K9F8008W0M-TIB0
Figure 6. Sequential Row Read2 Operation
R/B
I/O
Figure 7. Program & Read Status Operation
R/B
I/O
0
0
~
~
7
7
80H
50H
(A
Don t Care)
3
~ A
A
Address & Data Input
0
7
264 Byte Data
A
Start Add.(3Cycle)
~ A
:
0
~ A
7
& A
2
& A
8
~ A
8
~ A
19
19
t
R
10H
Data Field
Data Output
1st
21
t
PROG
Spare Field
6
t
R
) of the Status Register. Only the Read Status command
1st
2nd
Nth
Data Output
(8Byte)
70H
2nd
FLASH MEMORY
t
R
Fail
I/O
0
Data Output
(8Byte)
Nth
0
) may
Pass