PLL701-10XC PhaseLink Corp., PLL701-10XC Datasheet
PLL701-10XC
Manufacturer Part Number
PLL701-10XC
Description
Manufacturer
PhaseLink Corp.
Datasheet
1.PLL701-10XC.pdf
(8 pages)
Specifications of PLL701-10XC
Case
TSSOP16
Date_code
08+
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
The PLL701-10 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
Spread Spectrum Technology (SST) and permits
different levels of EMI reduction by selecting the
amplitude of the applied SST. The SST feature can
be turned off. An output enable input is also used.
The chip operates with input frequencies ranging from
13 to 30 MHz and provides 1x to 8x at its output.
OUTPUT CLOCK (FOUT) SELECTION
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
M2
0
0
0
0
1
1
1
1
XOUT
SD(0:1)
SC(0:3)
M(0:2)
Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
13MHz to 240MHz output with output enable.
13MHz to 30 MHz reference input frequency
accepted from crystal or external clock signal.
Reduced EMI from Spread Spectrum Modulation,
with selectable modulation amplitude for Center
Spread, Down Spread or Asymmetric Spread.
TTL/CMOS compatible outputs.
3.3V Operating Voltage.
150 ps maximum cycle-to-cycle jitter.
Available in 16-Pin 150mil SSOP or DIE.
XIN
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
XTAL
OSC
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
FIN/XIN
13 ~ 28
13 ~ 28
14 ~ 30
13 ~ 28
20 ~ 30
17 ~ 30
15 ~ 30
13 ~ 28
(MHz)
Control
Logic
SST
PLL
Multiplier
X1
X2
X3
X4
X5
X6
X7
X8
100 ~ 150
102 ~ 180
105 ~ 210
104 ~ 224
52 ~ 112
13 ~ 28
26 ~ 56
42 ~ 90
OE
FOUT
(MHz)
FOUT
PACKAGE PIN CONFIGURATION
DIE PAD CONFIGURATION
Note: ^: Internal pull-up resistor (120kΩ for SD0, 30 kΩ for SC0-
Y
XOUT/SD0*^
XOUT/SD0*^
X
GNDOSC
XIN/FIN
*: SD0 and SD1 are latched upon power-up.
SC2^
SC0^
SC1^
SC0^
SC1^
M2^
M1^
M0^
SC2, SD1, M0-M2 and OE). The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
M2^
M1^
M0^
XIN/FIN = 10 ~ 30 MHz
1
2
3
4
5
6
7
8
23
25
28
29
30
34
35
1
C501A
A0404
-04A
22
16
15
14
13
12
11
10
69 mil
9
PLL701-10
21
GND
AVDD
REF/SD1*^
VDD
SC3^
OE^
FOUT
GND
20
4
5
6
19
18
17
16
15
14
13
12
10
8
7
1700, 2540
AVDD
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
OE^
FOUT
GNDBUF
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