PL123S-09HSC PhaseLink Corp., PL123S-09HSC Datasheet
PL123S-09HSC
Manufacturer Part Number
PL123S-09HSC
Description
Manufacturer
PhaseLink Corp.
Datasheet
1.P123S-09H.pdf
(10 pages)
Specifications of PL123S-09HSC
Case
SOP16
Date_code
08+
FEATURES
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/9/08 Page 1
REF
Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123S-05
o 9 outputs PL123S-09
Zero input - output delay
Optional Drive Strength:
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP, SSOP or TSSOP
(PL123S-09), and 8-Pin SOP (PL123S-05) pack-
ages
Spread-compatible with spread-spectrum modula-
tion clock inputs
S1
S2
Standard (8mA) PL123S-05/-09
High (12mA)
(PL123S-09 Only)
PLL
Selector
Inputs
PL123S-05H/-09H
Mux
Spread-Compatible Low Skew Zero Delay Buffer
DESCRIPTION
The PL123S-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123S-05) or two (PL123S-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123S-09 allows control of the banks
of outputs by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
(Preliminary)
CLKA1
CLKA2
CLKB1
CLKB2
CLKA2
CLKA1
GND
VDD
GND
REF
REF
S2
1
2
3
4
5
6
7
8
1
2
3
4
16
15
14
13
12
11
10
8
7
6
5
9
CLKOUT
CLKA4
VDD
CLKA3
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
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