EDD51323DBH-5BLS-F ELPIDA [Elpida Memory], EDD51323DBH-5BLS-F Datasheet
EDD51323DBH-5BLS-F
Related parts for EDD51323DBH-5BLS-F
EDD51323DBH-5BLS-F Summary of contents
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... PRELIMINARY DATA SHEET 512M bits DDR Mobile RAM WTR (Wide Temperature Range), Low Power Function EDD51323DBH-LS (16M words 32 bits) Specifications Density: 512M bits Organization: 4M words 32 bits 4 banks Package: 90-ball FBGA Lead-free (RoHS compliant) and Halogen-free Power supply: VDD, VDDQ 1.7V to 1.95V Data rate: 400Mbps/333Mbps (max ...
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... Ordering Information Die Part number revision EDD51323DBH-5BLS-F D EDD51323DBH-6ELS-F Part Number Elpida Memory Type D: Monolithic Device Product Family D: DDR Mobile RAM Density / Bank 51: 512Mb / 4-bank Organization 32: x32 Power Supply, Interface 3: 1.8V, LVCMOS, w/ Low Power Function Preliminary Data Sheet E1432E20 (Ver. 2.0) ...
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... DQ6 VSSQ DQ3 DQ4 VDDQ DQ1 DQ2 VSSQ VDDQ DQ0 (Top view) Pin name CK /CK CKE VDD VSS VDDQ VSSQ NC 3 EDD51323DBH-LS 9 VDD VSSQ VDDQ VSSQ VDDQ VSS /RAS BA1 A1 A3 VDD Function Clock input Differential clock input Clock enable Power for internal circuit ...
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... CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................12 Pin Function.................................................................................................................................................13 Command Operation ...................................................................................................................................15 Simplified State Diagram .............................................................................................................................21 Operation of the DDR Mobile RAM .............................................................................................................22 Timing Waveforms.......................................................................................................................................46 Package Drawing ........................................................................................................................................57 Recommended Soldering Conditions..........................................................................................................58 Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS 4 ...
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... VDDQ 0.6 VID (DC) 0.4 VDDQ — VID (AC) 0.6 VDDQ — 0.7 VDDQ — VILD (DC) 0.3 — VIHD (AC) 0.8 VDDQ — VILD (AC) 0.3 — 5ns). 5ns). VDDQ and must track variations in the DC level of the same. 5 EDD51323DBH-LS Unit Note max. Unit Notes 1. VDDQ + 0.3 V 0.2 VDDQ V VDDQ + 0.3 V ...
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... Address inputs are SWITCHING, 50% data change each burst transfer CKE = H, tCK = tCK (min.), tRFC = tRFC (min.), 106 mA Address and control inputs are SWITCHING; Data bus inputs are STABLE Address and control inputs are STABLE Data bus inputs are STABLE 6 EDD51323DBH-LS Notes ...
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... All other input-only pins 2.0 — CK, /CK — — All other input-only pins — — DQ, DM, DQS 3.5 — DQ, DM, DQS — — 100MHz, VOUT = VDDQ/2, 7 EDD51323DBH-LS Condition Notes +40 C CKE = L +40 C < TJ +70 C CKE = L +70 C < TJ +85 C CKE = L Test condition Notes 0 VIN ...
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... Active to Read/Write delay tRCD Precharge to active command period tRP Column address to column address tCCD delay Active to active command period tRRD Write recovery time tWR Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS -5BLS -6ELS min. max. min. max. 5.0 — 6.0 — 0.45 0.55 0.45 ...
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... Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for tRP. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer. Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS -5BLS -6ELS min. max. ...
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... Test Condition (Wave form and Timing Reference) Preliminary Data Sheet E1432E20 (Ver. 2.0) Symbol Value VIH (AC) 0.8 VDDQ VIL (AC) 0.2 VDDQ VID (AC) 1.4 VIX (AC) VDDQ/2 with VDD=VDDQ SLEW VID VIX T VDDQ Output Load 10 EDD51323DBH-LS Unit Note V/ VIH VIL ( slew rate = T ...
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... BL BL/2 BL EDD51323DBH-LS 7.5ns min. max. Unit 3 + BL/2 tCK BL/2 tCK 2 + BL/2 tCK 3 tCK 3 tCK 3 + BL/2 tCK 3 tCK 1 tCK 2 tCK 0 tCK 2 tCK 16 tCK 10 tCK 1 tCK 1 tCK 2 tCK ...
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... Block Diagram CK /CK CKE Address, BA0, BA1 Mode register /CS /RAS /CAS /WE Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS Bank 3 Bank 2 Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit ...
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... Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Preliminary Data Sheet E1432E20 (Ver. 2.0) Address (A0 to A12) Organization Row address 32 bits AX0 to AX12 BA1 EDD51323DBH-LS Column address AY0 to AY8 ...
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... VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDD must be equal to VDDQ. Preliminary Data Sheet E1432E20 (Ver. 2.0) DQS Data mask DQS0 DM0 DQS1 DM1 DQS2 DM2 DQS3 DM3 14 EDD51323DBH-LS DQs DQ0 to DQ7 DQ8 to DQ15 DQ16 to DQ23 DQ24 to DQ31 ...
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... L H PRE PALL REF SELF MRS EMRS EDD51323DBH-LS BA1 BA0 AP Address ...
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... The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins in the mode register set cycle. For details, refer to "Mode register and extended mode register set". Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS BA1 L L ...
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... BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACT BA, A10 PRE, PALL DESL NOP BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACT BA, A10 PRE, PALL 17 EDD51323DBH-LS Operation NOP NOP 11 ILLEGAL* 11 ILLEGAL* 11 ILLEGAL* 11 ILLEGAL* NOP ILLEGAL NOP NOP NOP 11 ILLEGAL* 11 ILLEGAL* ...
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... BA, RA ACT BA, A10 PRE, PALL DESL NOP BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACT BA, A10 PRE/PALL 18 EDD51323DBH-LS Operation NOP NOP Burst stop Interrupting burst read operation to start new read 13 ILLEGAL* 11 ILLEGAL* Interrupting burst read operation to start pre-charge ILLEGAL NOP ...
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... DESL NOP BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRIT A BA, RA ACT BA, A10 PRE, PALL Minimum delay (Concurrent AP supported) BL/2 CL (rounded up)+ (BL/ (BL/2) + tWTR BL EDD51323DBH-LS Operation NOP NOP ILLEGAL 14 ILLEGAL* 14 ILLEGAL* 11, 14 ILLEGAL* 11, 14 ILLEGAL* ILLEGAL Units tCK tCK tCK tCK tCK tCK ...
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... This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle state. Power-down exit [PDEX] The DDR Mobile RAM can exit from power-down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS CKE n 1 ...
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... AUTO IDLE REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE CKE_ ROW ACTIVE BST READ WRITE READ READ WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 21 EDD51323DBH-LS Automatic sequence Manual input Deep power down exit sequence ...
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... Provide NOPs or DESL commands for at least tMRD time. 9. Using the MRS command, program the extended mode register for the desired operating modes. 10. Provide NOP or DESL commands for at least tMRD time. 11. The DRAM has been properly initialized and is ready for any valid command. Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS 22 ...
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... LMODE A3 Burst Type Sequential Interleave Reserved Reserved Reserved Reserved Mode Register Set 23 EDD51323DBH- Burst Length Reserved Reserved Reserved Reserved ...
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... Bank0 & Bank1 (BA1 = Bank0 (BA = BA1 = Extended Mode Register Set 24 EDD51323DBH- PASR Refresh Array All banks Reserved Reserved Reserved Reserved Reserved ...
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... CK /CK CKE Command PRE Note: Assume PRE and ACT command is closing and activating same bank. Preliminary Data Sheet E1432E20 (Ver. 2.0) NOP Power-down mode Power-Down Entry and Exit NOP NOP CKE Control 25 EDD51323DBH-LS 2 Valid* NOP 2 Valid Activate command, ACT ...
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... EDD51323DBH- 10, 11, 12, 13, 14 11, 10, 13, 12, 15, 14 10, 11 14, 15, 12, 13 11, 10 15, 14, 13, 12 12, 13, 14, 15 10, 11 13, 12, 15, 14 11, 10 14, ...
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... NOP tRPRE out0 out1 tRPST out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 27 EDD51323DBH-LS out out BL: Burst length ...
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... Read Operation (/CAS Latency) WRIT NOP Column tWPRE in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in0 in1 in2 in3 in4 in5 Write Operation 28 EDD51323DBH-LS t4.5 t5 t5.5 tRPST VTT VTT out3 in6 in7 in in in6 in7 14 15 BL: Burst length ...
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... The BST command is also supported for the burst write operation. No data will be written in subsequent cycles. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK Command READ DQS DQ Burst Stop during a Read Operation Preliminary Data Sheet E1432E20 (Ver. 2.0) t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ out0 out1 29 EDD51323DBH-LS t4.5 t5 t5.5 CL: /CAS latency ...
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... Note: Internal auto-precharge starts at the timing indicated by " Preliminary Data Sheet E1432E20 (Ver. 2.0) tRAS (min) tRP (min) BL/2 (= tRPD) READA NOP tAC,tDQSCK out0 ". Read with auto precharge NOP WL + BL/2 + tWR (= tWPD) in1 in2 in3 in4 ". Burst Write ( EDD51323DBH-LS ACT out1 out2 out3 tRP ACT ...
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... ACT command. tRCD after the ACT command, the consecutive read command can be issued. tn tn+1 tn+2 tn+3 READ READ out out A0 A1 Column = A Column = B Read Read Column = A Dout 31 EDD51323DBH-LS tn+4 tn+5 tn+6 NOP out out out out Column = B Dout Bank0 ...
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... READ to READ Command Interval (different bank)* Note Preliminary Data Sheet E1432E20 (Ver. 2.0) tn tn+1 tn+2 tn+3 READ READ NOP Column A Column B out A0 Column = A Column = B Read Read Bank0 Dout Bank0 Bank3 Read Read 32 EDD51323DBH-LS tn+4 tn+5 tn+6 NOP out out out out out Bank3 Dout ...
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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 33 EDD51323DBH-LS tn+5 tn+6 NOP Bank0 ...
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... NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E1432E20 (Ver. 2.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 34 EDD51323DBH-LS tn+3 tn+4 tn+5 NOP Bank0, 3 ...
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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued NOP WRIT tBSTZ (= CL) out0 out1 in0 in1 OUTPUT READ to WRITE Command Interval 35 EDD51323DBH- NOP in2 in3 INPUT ...
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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued READ tWTR* in2 in3 WRITE to READ Command Interval 36 EDD51323DBH- NOP out0 out1 out2 OUTPUT ...
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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP in2 out0 out1 out2 out3 37 EDD51323DBH- High-Z High ...
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... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 4 clock cycle] Preliminary Data Sheet E1432E20 (Ver. 2. NOP in2 in3 out0 out1 out2 out3 READ tWTR* in3 38 EDD51323DBH- High-Z High NOP out0 out1 out2 out3 ...
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... DQS Data will be written [WRITE to BST delay = 2 clock cycle] Preliminary Data Sheet E1432E20 (Ver. 2. in1 Following data will not be written BST NOP in2 in3 Following data will not be written. 39 EDD51323DBH- NOP longer longer ...
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... CK /CK Command WRIT NOP DM DQ in0 in1 DQS Data will be written [WRITE to BST delay = 3 clock cycle] Preliminary Data Sheet E1432E20 (Ver. 2. BST in2 in3 in4 in5 Following data will not be written. 40 EDD51323DBH- NOP longer ...
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... Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Preliminary Data Sheet E1432E20 (Ver. 2. PRE/ NOP PALL out0 out1 out2 out3 PRE/PALL NOP out0 out1 tHZP 41 EDD51323DBH- High-Z High-Z ...
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... The minimum interval tWPD is necessary between the write command and the precharge command /CK Command WRIT DM DQS DQ in0 in1 WRITE to PRECHARGE Command Interval (same bank) ( Preliminary Data Sheet E1432E20 (Ver. 2. PRE/PALL NOP tWPD tWR in2 in3 Last data input 42 EDD51323DBH- NOP ...
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... CK /CK Command WRIT DM DQS DQ in0 in1 Last data input WRITE to PRECHARGE Command Interval (same bank) ( mask data) Preliminary Data Sheet E1432E20 (Ver. 2. PRE/PALL NOP tWPD tWR in2 in3 Data masked 43 EDD51323DBH- NOP ...
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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD Mode Register Set to Bank Active 44 EDD51323DBH-LS NOP ACT NOP ROW: 0 Bank0 Active NOP ...
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... DM can mask input data. By setting DM to low, data can be written. When DM is set to high, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Preliminary Data Sheet E1432E20 (Ver. 2. Mask Mask Write mask latency = 0 DM Control 45 EDD51323DBH- ...
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... Command and Addresses Input Timing Definition CK /CK Command (/RAS, /CAS, /WE, /CS) Address Read Timing Definition (1) CK /CK Command READ High-Z DQ (Output) High-Z DQS Preliminary Data Sheet E1432E20 (Ver. 2.0) tIS tIH tIS tIH tLZ (min.) tLZ (min.) 46 EDD51323DBH-LS = Don't care tHZ (max.) High-Z High ...
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... Write Timing Definition tCK /CK CK tDQSS tWPRES DQS tWPRE DQ (Din) DM Preliminary Data Sheet E1432E20 (Ver. 2.0) tDQSCK tDSC tQH tDQSQ tDQSCK tDQSQ tDSS tDSH tDSC tDQSL tDQSH tDIPW tDS tDH tDS tDH tDIPW 47 EDD51323DBH-LS tQH tQHS Invalid tDSS tWPST tDIPW Don't care ...
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... Command is necessary Preliminary Data Sheet E1432E20 (Ver. 2.0) 2 refresh cycles are necessary tRP tRFC tRFC Auto-Refresh Auto-Refresh Command Command is necessary is necessary 48 EDD51323DBH-LS Address key Address key tMRD tMRD Mode Extended Activate Register Set Mode Command Command Register Set is necessary Command ...
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... Bank 0 Bank 0 Bank 0 Bank 0 Read Read Precharge Precharge 49 EDD51323DBH-LS tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = Don't care ...
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... Bank 0 Precharge 50 EDD51323DBH-LS tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH Bank0 Access = Don't care ...
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... Bank 3 Read Precharge Active T10 R:b C Read Write tRWD tWRD Bank 3 Bank 3 Active Write 51 EDD51323DBH-LS T10 T11 T12 T13 T14 T15 Don't care T11 Tn Tn+1 Tn+2 Tn+3 Tn+4 C:b'' b’’ Read Bank 3 Read Read cycle Don't care ...
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... Auto-Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM High-Z DQS High-Z DQ tRP Precharge Auto If needed Refresh Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH- tRFC Bank 0 Bank 0 Active Read Don't care ...
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... Self-Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ tRP Precharge Self refresh If needed entry Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS tIH CKE = low R: b tSREX Bank 0 Self refresh Active exit Bank 0 Read Don't care ...
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... Power-Down Entry and Exit /CK CK CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ tRP Precharge If needed Preliminary Data Sheet E1432E20 (Ver. 2. CKE = low tCKE R: b tPDEX tPDEN Power down Power Bank 0 entry down Active exit 54 EDD51323DBH- Bank 0 Read Don't care ...
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... Deep Power-Down Entry /CK CKE /CS /RAS /CAS /WE BA0 BA1 A10 Address DM High-Z DQ tRP Precharge Deep All Banks Power Down Command Entry Preliminary Data Sheet E1432E20 (Ver. 2.0) Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 55 EDD51323DBH-LS Tn+6 = Don't care ...
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... Note: The sequence of auto-refresh, mode register programming and extended mode register programming above may be transposed. Preliminary Data Sheet E1432E20 (Ver. 2.0) tMRD tMRD Address key tRFC Extended CBR (Auto) CBR (Auto) Mode Refresh Refresh Register Set Command Command Command is necessary is necessary is necessary 56 EDD51323DBH-LS 2 refresh cycles are necessary tRFC Activate Command = Don't care ...
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... Package Drawing 90-ball FBGA Solder ball: Lead free (Sn-Ag-Cu INDEX MARK Preliminary Data Sheet E1432E20 (Ver. 2.0) 8.0 ± 0.1 0 INDEX MARK 0.2 S 1.0 max. S 0.35 ± 0.05 φ0. 90-φ0.45 ± 0.05 1.6 0.8 6.4 57 EDD51323DBH-LS Unit: mm ECA-TS2-0238-01 ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD51323DBH. Type of Surface Mount Device EDD51323DBH: 90-ball FBGA < Lead free (Sn-Ag-Cu) > Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS 58 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH-LS 59 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E1432E20 (Ver. 2.0) EDD51323DBH- ...