STAC9202D3TAEYY IDT [Integrated Device Technology], STAC9202D3TAEYY Datasheet - Page 31
STAC9202D3TAEYY
Manufacturer Part Number
STAC9202D3TAEYY
Description
2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.STAC9202D3TAEYY.pdf
(135 pages)
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IDT™
STAC9202
2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH DUAL DIGITAL MICROPHONE INTERFACES
2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH DUAL DIGITAL MICROPHONE INTERFACES
5.4.13.
AFG GPIOEn
[31:4]
Bit
Bit
[1]
[0]
[3]
[2]
Set1
Get
Bitfield Name
Bitfield Name
Mask3
Mask2
Data1
Data0
Rsvd
Table 35. AFG GPIOEn Command Response Format
Table 33. AFG GPIO Command Response Format
Table 34. AFG GPIOEn Command Verb Format
Verb ID
IDT CONFIDENTIAL
F16
716
RW
RW
RW
RW
RW
RW
R
See bits [7:0] of bitfield table
Reset
Reset
0x0
0x0
0x0
0x0
0x0
Payload
Data for GPIO1 (Pin 34). If this GPIO bit is
configured as Sticky (edge-sensitive) input,
it can be cleared by writing zero (one) here
when the corresponding Polarity Control bit
is zero (one).
Data for GPIO0 (Pin 33). If this GPIO bit is
configured as Sticky (edge-sensitive) input,
it can be cleared by writing zero (one) here
when the corresponding Polarity Control bit
is zero (one).
00
Reserved
Enable for GPIO3:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
Enable for GPIO2:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
31
STAC9202
Description
Description
See bitfield table
0000_0000h
Response
PC AUDIO
V 1.1 102606
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