A3P250-FG144 Actel, A3P250-FG144 Datasheet

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A3P250-FG144

Manufacturer Part Number
A3P250-FG144
Description
Manufacturer
Actel
Datasheet

Specifications of A3P250-FG144

Case
BGA
Date_code
0709+

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February 2008
© 2008 Actel Corporation
ProASIC3 Flash Family FPGAs
with Optional Soft ARM
Features and Benefits
High Capacity
Reprogrammable Flash Technology
High Performance
In-System Programming (ISP) and Security
Low Power
High-Performance Routing Hierarchy
Advanced I/O
ProASIC3 Product Family
ProASIC3 Devices
ARM7 Devices
Cortex-M1 Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. Refer to the
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the
5. The M1A3P250 device does not support this package.
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
• Segmented, Hierarchical Routing and Clock Structure
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
QFN
VQFP
TQFP
PQFP
FBGA
† A3P015 and A3P030 devices do not support this feature.
Standard (AES) Decryption (except ARM-enabled ProASIC
devices) via JTAG (IEEE 1532–compliant)
®
1
to Secure FPGA Contents
CoreMP7
2
3
1
datasheet or
A3P015
QN68
15 k
128
384
1 k
49
6
2
Cortex-M1
®
A3P030
QN132
VQ100
Support
30 k
256
768
1 k
81
6
2
product brief for more information.
A3P060
QN132
VQ100
TQ144
FG144
1,536
60 k
512
Yes
1 k
18
18
96
4
1
2
®
3
‡ Supported only by A3P015 and A3P030 devices.
A3P125
QN132
VQ100
TQ144
PQ208
FG144
125 k
1,024
3,072
133
Yes
1 k
Clock Conditioning Circuit (CCC) and PLL
Embedded Memory
ARM Processor Support in ProASIC3 FPGAs
36
18
8
1
2
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
• True Dual-Port SRAM (except ×18)
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
ProASIC3E Flash Family FPGAs
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
2.5 V / 5.0 V Input
M-LVDS (A3P250 and above)
Capabilities and External Feedback
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
Processor Available with or without Debug
FG144/256
M1A3P250
QN132
A3P250
VQ100
PQ208
250 k
6,144
157
Yes
1 k
36
18
8
1
4
5
5
I/O
M1A3P400
FG144/256/
Phase-Shift,
A3P400
PQ208
400 k
9,216
Standards:
194
484
Yes
1 k
54
12
18
1
4
handbook.
M1A3P600
FG144/256/
Multiply/Divide,
LVTTL,
A3P600
and Drive Strength
13,824
PQ208
600 k
108
235
484
Yes
1 k
24
18
1
4
LVCMOS
M1A3P1000
M7A3P1000
and LVCMOS
FG144/256/
A3P1000
24,576
PQ208
1 M
144
300
484
Yes
1 k
32
18
1
4
v1.0
3.3 V /
Delay
®
I

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