74LVC595ABQ,115 NXP Semiconductors, 74LVC595ABQ,115 Datasheet - Page 12
74LVC595ABQ,115
Manufacturer Part Number
74LVC595ABQ,115
Description
IC 8BIT SHIFT REGISTER 16HVQFN
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
Not Requiredr
Datasheet
1.74LVC595ABQ115.pdf
(19 pages)
Specifications of 74LVC595ABQ,115
Package / Case
16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
Logic Type
Shift Register
Output Type
Standard
Function
Serial to Parallel
Number Of Elements
1
Number Of Bits Per Element
8
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counting Sequence
Serial to Serial/Parallel
Number Of Circuits
1
Logic Family
LVC
Propagation Delay Time
4.7 ns, 4 ns
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Technology
CMOS
Number Of Elements
1
Number Of Bits
8
Logical Function
Shift Register
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Temp Range
-40C to 125C
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC595ABQ-G
74LVC595ABQ-G
935282468115
74LVC595ABQ-G
935282468115
NXP Semiconductors
Table 8.
74LVC595A_1
Product data sheet
Supply voltage
V
V
V
Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the
Fig 12. 3-state enable and disable times
CC
CC
CC
< 2.7 V
2.7 V
Measurement points are given in
V
master reset to shift clock (SHCP) recovery time
Measurement points are given in
V
OL
OL
Measurement points
and V
and V
OH
OH
are typical output voltage drops that occur with the output load.
are typical output voltage drops that occur with the output load.
HIGH-to-OFF
OFF-to-HIGH
OFF-to-LOW
LOW-to-OFF
OE input
output
output
Input
V
0.5
1.5 V
M
SH CP input
Q 7 S output
MR input
V
CC
Table
Table
GND
GND
V
V
V
CC
OH
OL
V
GND
GND
V
I
V
OH
OL
8.
8.
V
V
I
I
V
Rev. 01 — 29 May 2007
M
enabled
outputs
V
t
8-bit serial-in/serial-out or parallel-out shift register; 3-state
PLZ
Output
V
0.5
1.5 V
t
M
PHZ
M
t
t
PHL
W
V
CC
V
X
V
V
t
M
Y
rec
V
M
disabled
outputs
V
V
V
t
X
OL
OL
PZL
t
PZH
0.15 V
0.3 V
mna561
V
M
V
M
001aae821
outputs
enabled
74LVC595A
V
V
V
Y
OH
OH
© NXP B.V. 2007. All rights reserved.
0.15 V
0.3 V
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