ISPLSI2064VE-100LJ44 Lattice Semiconductor Corp., ISPLSI2064VE-100LJ44 Datasheet
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ISPLSI2064VE-100LJ44
Manufacturer Part Number
ISPLSI2064VE-100LJ44
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheets
1.ISPLSI2064VE-100LJ44.pdf
(15 pages)
2.ISPLSI2064VE-200LT100.pdf
(17 pages)
3.ISPLSI2064VE-200LT100.pdf
(15 pages)
Specifications of ISPLSI2064VE-100LJ44
Case
PLCC
Date_code
00+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPLSI2064VE-100LJ44
Manufacturer:
LATTICE
Quantity:
5 510
Company:
Part Number:
ISPLSI2064VE-100LJ44
Manufacturer:
MOT
Quantity:
5 510
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
• HIGH-PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
*Advanced Information
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064ve_06
Features
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
— Interfaces with Standard 5V TTL Devices
—
—
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— 3.3V In-System Programmability (ISP™) Using
— Open-Drain Output Option for Flexible Bus Interface
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
f
t
Boundary Scan Test Access Port (TAP)
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
Market and Improved Product Quality
Machines, Address Decoders, etc.
ispLSI 2064V Devices
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 280MHz* Maximum Operating Frequency
pd = 3.5ns* Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2064VE is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VE features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VE offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
A0
A2
A3
A1
High Density SuperFAST™ PLD
A4
GLB
ispLSI
3.3V In-System Programmable
Output Routing Pool (ORP)
B7
A5
Global Routing Pool
Output Routing Pool (ORP)
Logic
Array
Input Bus
(GRP)
D Q
D Q
D Q
D Q
B6
Input Bus
A6
®
B5
A7
2064VE
September 2000
B4
B0
B3
B2
B1
0139A/2064V