ISPLSI2032A-135LT44 Lattice Semiconductor Corp., ISPLSI2032A-135LT44 Datasheet
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ISPLSI2032A-135LT44
Manufacturer Part Number
ISPLSI2032A-135LT44
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.ISPLSI2032A-135LT44.pdf
(16 pages)
Specifications of ISPLSI2032A-135LT44
Case
QFP44
Date_code
04+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPLSI2032A-135LT44
Manufacturer:
LATTICE
Quantity:
88
Part Number:
ISPLSI2032A-135LT44
Manufacturer:
LATTICE
Quantity:
20 000
• ENHANCEMENTS
• HIGH DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032_11
Features
— ispLSI 2032A is Fully Form and Function Compatible
— ispLSI 2032A is Built on an Advanced 0.35 Micron
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
—
—
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
— Lead-Free Package Options
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
E
Machines, Address Decoders, etc.
f
t
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 180 MHz Maximum Operating Frequency
pd = 5.0 ns Propagation Delay
2
CMOS
®
Technology
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
A0
A1
A2
A3
GLB
ispLSI
Global Routing Pool
Logic
Array
(GRP)
D Q
D Q
D Q
D Q
®
2032/A
August 2006
A7
A6
A5
A4
0139Bisp/2000