MM74HCT373N Fairchild Semiconductor, MM74HCT373N Datasheet - Page 5
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MM74HCT373N
Manufacturer Part Number
MM74HCT373N
Description
IC LATCH OCTAL D 3 STATE 20-DIP
Manufacturer
Fairchild Semiconductor
Series
74HCTr
Datasheet
1.MM74HCT374N.pdf
(10 pages)
Specifications of MM74HCT373N
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
25ns
Current - Output High, Low
7.2mA, 7.2mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Number Of Circuits
8
Logic Family
74HCT
Polarity
Non-Inverting
Input Bias Current (max)
1000 uA
High Level Output Current
- 7.2 mA
Low Level Output Current
7.2 mA
Propagation Delay Time
40 ns at 5 V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MM74HCT373N
Manufacturer:
AT
Quantity:
280
Part Number:
MM74HCT373N
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
C
PHL
PHL
PZH
PHZ
W
S
H
PHL
PHL
PZH
PHZ
THL
W
S
H
Symbol
AC Electrical Characteristics
MM74HCT373: V
AC Electrical Characteristics
MM74HCT373: V
Note 5: C
I
IN
OUT
PD
S
, t
, t
, t
, t
, t
, t
, t
, t
, t
Symbol
C
TLH
PLH
PLH
PZL
PLZ
PLH
PLH
PZL
PLZ
PD
V
PD
CC
Maximum Propagation
Delay Data to Output
Maximum Propagation Delay
Latch Enable to Output
Maximum Enable Propagation
Delay Control to Output
Maximum Disable Propagation
Delay Control to Output
Maximum Output Rise
and Fall Time
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 5)
determines the no load dynamic power consumption, P
f
I
CC
CC
CC
Maximum Propagation Delay
Data to Output
Maximum Propagation Delay
Latch Enable to Output
Maximum Enable Propagation Delay
Control to Output
Maximum Disable Propagation Delay
Control to Output
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
.
Parameter
5.0V, t
5.0V
r
r
10%, t
Parameter
t
f
6 ns T
r
t
f
A
6 ns (unless otherwise specified)
C
C
C
C
C
C
R
C
R
C
OC
OC
25
L
L
L
L
L
L
L
L
L
L
q
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
50 pF
1 k
C (unless otherwise specified)
50 pF
V
GND
CC
Conditions
:
:
C
C
C
R
C
R
L
L
L
L
L
L
D
45 pF
45 pF
45 pF
1 k
5 pF
1 k
C
:
:
PD
V
Conditions
CC
5
2 f
I
CC
Typ
22
30
25
32
21
30
21
8
V
T
CC
A
, and the no load dynamic current consumption,
25
q
C
30
40
35
45
30
40
30
12
16
10
10
20
52
5
5
T
A
Guaranteed Limits
Typ
18
21
20
18
40 to 85
37
50
44
56
37
50
37
15
20
13
10
20
6
q
C T
Guaranteed
Limit
A
25
30
28
25
16
10
www.fairchildsemi.com
5
55 to 125
45
60
53
68
45
60
45
18
24
20
10
20
8
q
C
Units
ns
ns
ns
ns
ns
ns
ns
Units
pF
pF
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns