GAL16VP8B25LJ Lattice Semiconductor Corp., GAL16VP8B25LJ Datasheet
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GAL16VP8B25LJ
Manufacturer Part Number
GAL16VP8B25LJ
Description
PLCC20
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.GAL16VP8B25LJ.pdf
(17 pages)
Specifications of GAL16VP8B25LJ
Date_code
10+
• HIGH DRIVE E
• ENHANCED INPUT AND OUTPUT FEATURES
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations.
Semiconductor's advanced E
CMOS with Electrically Erasable (E
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL16VP8
combines the familiar GAL16V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus driving capability.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16vp8_03
Features
Description
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL16V8
— 100% Functional Testability
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control
2
CELL TECHNOLOGY
The GAL16VP8 is manufactured using Lattice
®
2
Advanced CMOS Technology
CMOS
®
GAL
2
®
CMOS process which combines
DEVICE
2
) floating gate technology. High
1
Functional Block Diagram
Pin Configuration
I
Vcc
I
I
I
I
I
I
I I
I/CLK
I
I
I
I
4
6
8
I
9
I
GAL16VP8
Top View
I/OE
2
I
PLCC
I/CLK
I/O/Q
11
I/O/Q
20
I
I/O/Q
I/O/Q
13
High-Speed E
18
16
14
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
GAL16VP8
Generic Array Logic™
8
8
8
8
8
8
8
8
I/CLK
Vcc
I/OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
CLK
1
5
10
December 1997
16VP8
OE
2
GAL
DIP
CMOS PLD
20
11
15
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I