EVAL-AD7713EB AD [Analog Devices], EVAL-AD7713EB Datasheet

EVAL-AD7713EB

Manufacturer Part Number

EVAL-AD7713EB

Description

LC2MOS Loop-Powered Signal Conditioning ADC

Manufacturer

AD [Analog Devices]

Datasheet

1.EVAL-AD7713EB.pdf (28 pages)

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GENERAL DESCRIPTION

The AD7713 is a complete analog front end for low frequency

measurement applications. The device accepts low level signals

directly from a transducer or high level signals (4 V

outputs a serial digital word. It employs a sigma-delta con-

version technique to realize up to 24 bits of no missing codes

performance. The input signal is applied to a proprietary pro-

grammable gain front end based around an analog modulator.

The modulator output is processed by an on-chip digital filter.

The first notch of this digital filter can be programmed via the

on-chip control register allowing adjustment of the filter cutoff

and settling time.

The part features two differential analog inputs and one single-

ended high level analog input as well as a differential reference

input. It can be operated from a single supply (AV

at +5 V). The part provides two current sources which can be

used to provide excitation in three-wire and four-wire RTD con-

figurations. The AD7713 thus performs all signal conditioning

and conversion for a single, dual or three-channel system.

The AD7713 is ideal for use in smart, microcontroller-based

systems. Gain settings, signal polarity and RTD current control

can be configured in software using the bidirectional serial port.

The AD7713 contains self-calibration, system calibration and

background calibration options and also allows the user to read

and to write the on-chip calibration registers.

*Protected by U.S. Patent No. 5,134,401.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

Charge Balancing ADC

Three-Channel Programmable Gain Front End

Low-Pass Filter with Programmable Filter Cutoffs

Ability to Read/Write Calibration Coefficients

Bidirectional Microcontroller Serial Interface

Single Supply Operation

Low Power (3.5 mW typ) with Power-Down Mode

APPLICATIONS

Loop Powered (Smart) Transmitters

RTD Transducers

Process Control

Portable Industrial Instruments

24 Bits No Missing Codes

(150 W typ)

Gains from 1 to 128

Two Differential Inputs

One Single Ended High Voltage Input

0.0015% Nonlinearity

REF

and DV

Loop-Powered Signal Conditioning ADC

) and

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

CMOS construction ensures low power dissipation and a hard-

ware programmable power-down mode reduces the standby

power consumption to only 150 W typical. The part is avail-

able in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line

package (DIP) as well as a 24-lead small outline (SOIC) package.

PRODUCT HIGHLIGHTS

1. The AD7713 consumes less than 1 mA in total supply cur-

2. The two programmable gain channels allow the AD7713 to

3. No Missing Codes ensures true, usable, 24-bit dynamic

4. The AD7713 is ideal for microcontroller or DSP processor

AIN2(+)

AIN1(+)

AIN1(–)

AIN2(–)

RTD1

RTD2

AIN3

rent, making it ideal for use in loop-powered systems.

accept input signals directly from a transducer removing a

considerable amount of signal conditioning. To maximize the

flexibility of the part, the high level analog input accepts

for three-wire and four-wire RTD configurations.

range coupled with excellent 0.0015% accuracy. The effects

of temperature drift are eliminated by on-chip self-calibration,

which removes zero-scale and full-scale errors.

applications with an on-chip control register which allows

control over filter cutoff, input gain, signal polarity and cali-

bration modes. The AD7713 allows the user to read and

write the on-chip calibration registers.

REF

SCALING

AGND

INPUT

200µA

signals. On-chip current sources provide excitation

FUNCTIONAL BLOCK DIAGRAM

200µA

DGND

1µA

IN(–)

REF

A = 1 – 128

RFS

PGA

IN(+)

REF

TFS

CONTROL

SERIAL INTERFACE

MODE SDATA SCLK

CHARGING BALANCING A/D

AUTO-ZEROED

MODULATOR

BIAS

CONVERTER

AD7713*

GENERATION

OUTPUT

AD7713

CLOCK

DIGITAL

Fax: 617/326-8703

FILTER

DRDY

STANDBY

MOS

MCLK

OUT

SYNC

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EVAL-AD7713EB Summary of contents

Page 1

FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Three-Channel Programmable Gain Front End Gains from 1 to 128 Two Differential Inputs One Single Ended High Voltage Input Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write ...

Page 2

AD7713–SPECIFICATIONS MCLK MHz unless otherwise noted. All specifications T Parameter A, S Versions STATIC PERFORMANCE No Missing Codes Output Noise See Tables I & II Integral Nonlinearity 2, 3 Positive Full-Scale Error ...

Page 3

Parameter A, S Versions REFERENCE INPUT REF IN(+) – REF IN(–) Voltage +2 Input Sampling Rate CLK IN 6 Normal-Mode 50 Hz Rejection 100 6 Normal-Mode 60 Hz Rejection 100 Common-Mode Rejection (CMR) 100 6 ...

Page 4

AD7713–SPECIFICATIONS Parameter A, S Versions POWER REQUIREMENTS Power Supply Voltages AV Voltage + Voltage +5 DD Power Supply Currents AV Current 0.6 DD 0.7 DV Current 0 Power Supply Rejection (AV and ...

Page 5

Limit at T Parameter (A, S Versions) External-Clocking Mode SCLK CLK CLK CLK ...

Page 6

... Therefore, proper precautions are recommended to avoid any performance degradation or loss of functionality. Model AD7713AN AD7713AR AD7713AQ AD7713SQ EVAL-AD7713EB *N = Plastic DIP Cerdip SOIC. Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C Plastic DIP Package, Power Dissipation . . . . . . . . . . . 450 mW Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 105 C/W JA Lead Temperature, Soldering (10 sec +260 C Cerdip Package, Power Dissipation ...

Page 7

Pin Mnemonic Function 1 SCLK Serial Clock. Logic input/output depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes ...

Page 8

AD7713 Pin Mnemonic Function 21 DRDY Logic output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used ...

Page 9

A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the contents of the control register. The control register is 24 bits wide ...

Page 10

AD7713 PGA Gain Gain (Default Condition After the Internal Power-On Reset ...

Page 11

Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar in- put ranges with +2.5 V. These numbers are typical and are generated ...

Page 12

AD7713 Figure 2 gives similar information to that outlined in Table I. In this plot, the output rms noise is shown for the full range of avail- able cutoff frequencies rather than for some typical cutoff frequencies as in Tables ...

Page 13

The AD7713 gives the user access to the on-chip calibration registers allowing the microprocessor to read the device’s cali- bration coefficients and also to write its own calibration coeffi- cients to the part from prestored values in E the microprocessor ...

Page 14

AD7713 DIGITAL FILTERING The AD7713’s digital filter behaves like a similar analog filter, with a few minor differences. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion pro- cess. Analog filtering ...

Page 15

Both inputs of the differential input channels look into similar input circuitry. In any case, the error introduced due to longer charging times is a gain error which can be removed using the system calibration ...

Page 16

AD7713 voltage can with no degradation in performance provided that the absolute value of REF IN(+) and REF IN(–) does not exceed its AV and AGND limits. The part is also DD functional with V voltages ...

Page 17

The AD7713 also provides the facility to write to the on-chip calibration registers, and in this manner the span and offset for the part can be adjusted by the user. The offset calibration regis- ter contains a value which is ...

Page 18

AD7713 Cal Type MD2, MD1, MD0 Self-Cal System Cal System Cal System Offset Cal Background Cal Span and Offset Limits Whenever a system calibration mode ...

Page 19

DIGITAL INTERFACE The AD7713’s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers and digital signal processors. A serial read to the AD7713 can access data from the output register, the control register or ...

Page 20

AD7713 A0 (I) TFS (I) SCLK (O) SDATA (I) Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation Write Operation Data can be written to either the control register or calibration registers. In either case, the write operation is not affected ...

Page 21

DRDY (O) A0 (I) RFS (I) SCLK (I) SDATA (O) Figure 12a. External Clocking Mode, Output Data Read Operation DRDY (O) A0 (I) RFS (I) SCLK (I) SDATA (O) Figure 12b. External Clocking Mode, Output Data Read Operation ( RFS ...

Page 22

AD7713 A0 (I) TFS (I) SCLK (I) SDATA (I) Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation ( TFS Returns High During Write Operation) Data to be loaded to the AD7713 must be valid prior to the ris- ing ...

Page 23

A read operation to the control/calibration registers is similar, but in this case the status of DRDY can be ignored. The A0 line is brought low when ...

Page 24

AD7713 READ 1: MOV A,SBUF; Read Buffer RLC A; Rearrange Data MOV B.0,C; Reverse Order of Bits RLC A; MOV B.1,C; RLC A; MOV B.2,C; RLC A; MOV B.3,C; RLC A; MOV B.4,C; RLC A; MOV B.5,C; RLC A; MOV ...

Page 25

APPLICATIONS Four-Wire RTD Configurations Figure 20 shows a four-wire RTD application where the RTD transducer is interfaced directly to the AD7713. In the four-wire configuration, there are no errors associated with lead resis- tances as no current flows in the ...

Page 26

AD7713 OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE AD7710 FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Two-Channel Programmable Gain Front End Gains from 1 to 128 Differential Inputs Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write ...

Page 27

AD7712 FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity High Level and Low Level Analog Input Channels Programmable Gain for Both Inputs Gains from 1 to 128 Differential Input for Low Level Channel Low-Pass Filter with Programmable ...

Page 28

AD7713 24 1 0.210 (5.33) MAX SEATING PLANE 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.005 (0.13) MIN 24 1 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 15.6 (0.614) 15.2 (0.598 0.050 (1.27) ...

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