HIP6020ACB Intersil Corporation, HIP6020ACB Datasheet - Page 8

• Manufacturer Part Number: HIP6020ACB
• Description: Advanced Dual PWM and Dual Linear Power Controller
• Manufacturer: Intersil Corporation

The remaining outputs are also programmed to follow the SS
pin voltage. The PGOOD signal toggles ‘high’ when all output
voltage levels have exceeded their under-voltage levels. See
the Soft-Start Interval section under Applications Guidelines
for a procedure to determine the soft-start interval.
Fault Protection
All four outputs are monitored and protected against extreme
overload. A sustained overload on any output or an over-
voltage on V
drives the FAULT/RT pin to VCC.
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC1 and OC2), linear
under-voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C
fully charged to 4.5V (UP signal). An under-voltage on either
linear output (sensed at FB3 and FB4) is ignored until after
the soft-start interval (T4 in Figure 6). This allows V
and V
bias input voltage (+12V
resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short across the synchronous PWM
upper MOSFET (Q1) causes V
output exceeds the over-voltage threshold of 115% of
DACOUT, the over-voltage comparator trips to set the fault
latch and turns the lower MOSFET (Q2) on. This blows the
input fuse and reduces V
FAULT/RT pin to VCC.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.
LUV
OC1
OC2
OV
SS
0.15V
FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
OUT4
+
-
+
-
to increase without fault at start-up. Cycling the
OUT1
CURRENT
UP
LATCH
OVER-
output (VSEN1) disables all outputs and
S
R
Q
POR
IN
OUT1
on the VCC pin off then on)
4-8
. The fault latch raises the
R
OUT1
COUNTER
to increase. When the
INHIBIT
LATCH
FAULT
S
R
Q
OUT3
VCC
SS
FAULT
is
HIP6020A
Over-Current Protection
All outputs are protected against excessive over-currents.
Both PWM controllers use the upper MOSFET’s on-
resistance, r
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 8 illustrates the over-current protection with an
overload on OUT2. The overload is applied at T0 and the
current increases through the inductor (L
the OVER-CURRENT2 comparator trips when the voltage
across Q3 (i
R
capacitor (C
counter. C
with the error amplifiers clamped by soft-start. With OUT2 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4.5V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4.5V at T4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.
The PWM1 controller operates in the same way as PWM2 to
over-current faults. Additionally, the two linear controllers
monitor the FB pins for an under-voltage. Should excessive
currents cause FB3 or FB4 to fall below the linear under-
voltage threshold, the LUV signal sets the over-current latch,
providing C
the C
above the under-voltage threshold during normal operation.
Cycling the bias input power off then on resets the counter
and the fault latch.
OCSET
10V
SS
0A
0V
4V
2V
0V
. This inhibits all outputs, discharges the soft-start
charge interval allows the linear outputs to build
SS
FIGURE 5. OVER-CURRENT OPERATION
SS
D
SS
T0
DS(ON)
COUNT
recharges at T2 and initiates a soft-start cycle
•
) with a 28 A current sink, and increments the
is fully charged. Blanking the LUV signal during
= 1
OVERLOAD
T1
r
DS(ON)
APPLIED
to monitor the current for protection
) exceeds the level programmed by
T2
COUNT
TIME
= 2
REPORTED
FAULT
OUT2
T3
). At time T1,
COUNT
= 3
T4