HIP6020ACB Intersil Corporation, HIP6020ACB Datasheet - Page 10

• Manufacturer Part Number: HIP6020ACB
• Description: Advanced Dual PWM and Dual Linear Power Controller
• Manufacturer: Intersil Corporation

NOTE: 0 = connected to GND, 1 = open or connected to 5V through
pull-up resistors
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s output
of the PWM converters. This generates PHASE pulses of
increasing width that charge the output capacitor(s). After the
output voltage increases to approximately 70% of the set value,
the reference input of the error amplifier is clamped to a voltage
proportional to the SS pin voltage. The resulting output voltages
start-up as shown in Figure 6.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval
and the surge current are programmed by the soft-start
capacitor, C
increases the peak surge current. The peak surge current
occurs during the initial output voltage rise to 70% of the set
value. Using the recommended 0.1 F soft start capacitor
insures all output voltages ramp up to their set values within
10ms of the input voltages reaching POR levels.
Shutdown
Neither PWM output switches until the soft-start voltage
(V
reference on each linear’s amplifier is clamped to the soft-
start voltage. Holding the SS pin low (with an open drain or
open collector signal) turns off all four regulators.
SS
VID4
1
1
1
1
1
1
) exceeds the oscillator’s valley voltage. Additionally, the
TABLE 1. OUT1 VOLTAGE PROGRAM (Continued)
SS
VID3
0
0
0
0
0
0
. Programming a faster soft-start interval
PIN NAME
VID2
1
1
0
0
0
0
4-10
VID1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
NOMINAL
VOLTAGE
DACOUT
3.0
3.1
3.2
3.3
3.4
3.5
HIP6020A
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-off
transition of the upper MOSFET. Prior to turn-off, the upper
MOSFET was carrying the full load current. During the turn-
off, current stops flowing in the upper MOSFET and is picked
up by the lower MOSFET or Schottky diode. Any inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection,
tight layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using a HIP6020A controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic de-coupling capacitors, close to the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node, since the internal current source is only 28 A.
A multi-layer printed circuit board is recommended. Figure
10 shows the connections of the critical components in the
converter. Note that the capacitors C
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages, the
stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise. Use
the remaining printed circuit layers for small signal wiring.
The wiring traces from the control IC to the MOSFET gate
and source should be sized to carry 2A peak currents.
IN
and C
OUT
SS
each
. Locate