CY62128V Cypress Semiconductor, CY62128V Datasheet - Page 6
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CY62128V
Manufacturer Part Number
CY62128V
Description
128K x 8 Static RAM
Manufacturer
Cypress Semiconductor
Datasheet
1.CY62128V.pdf
(12 pages)
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Switching Waveforms
Read Cycle No. 1
Read Cycle No. 2 (OE Controlled)
Write Cycle No. 1 (CE
Notes:
DATA OUT
10. Device is continuously selected. OE, CE = V
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE
13. Data I/O is high impedance if OE = V
14. If CE
ADDRESS
DATA I/O
CURRENT
DATA OUT
ADDRESS
ADDRESS
SUPPLY
CE
CE
WE
CE
CE
V
OE
1
CC
1
2
goes HIGH or CE
1
2
[10, 11]
2
PREVIOUS DATA VALID
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
HIGH IMPEDANCE
or CE
t
PU
t
2
LZCE
Controlled)
IH
.
[11, 12]
t
t
ACE
LZOE
1
IL,
t
SA
transition LOW and CE
CE
t
50%
OHA
t
DOE
2
=V
[13,14]
IH
.
t
AA
t
AW
2
t
transition HIGH.
RC
t
WC
6
t
PWE
t
RC
DATA VALID
t
SCE
t
t
SD
SCE
DATA VALID
t
HD
t
DATA VALID
HZOE
t
HA
CY62128V Family
t
HZCE
t
PD
50%
IMPEDANCE
HIGH
62128V–8
62128V-9
62128V-10
I
I
CC
SB