CY62128V Cypress Semiconductor, CY62128V Datasheet - Page 5
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CY62128V
Manufacturer Part Number
CY62128V
Description
128K x 8 Static RAM
Manufacturer
Cypress Semiconductor
Datasheet
1.CY62128V.pdf
(12 pages)
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Switching Characteristics
Data Retention Current Graph
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
5.
6.
7.
8.
9.
Parameter
Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
At any given temperature and voltage condition, t
t
The internal write time of the memory is defined by the overlap of CE
write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
OL
HZOE
/I
OH
, t
HZCE
and 100-pF load capacitance.
, and t
[8, 9]
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
are specified with C
Description
Over the Operating Range
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
[6]
[6]
(for “L” version only)
[6, 7]
[6]
[6, 7]
[6, 7]
HZCE
is less than t
80
70
60
40
30
50
20
10
0
DATA RETENTION
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
LZCE
Min. Max. Min. Max.
1
[5]
62128V-55
55
10
10
55
45
45
45
25
, t
LOW, CE
5
0
0
0
0
5
T =25 C
HZOE
A
5
is less than t
2
55
55
20
20
20
55
20
HIGH, and WE LOW. CE
HZWE
62128V-70
CURRENT
70
10
10
10
70
60
60
55
30
LZOE
0
0
0
0
5
and t
, and t
SD
70
70
35
25
25
70
25
.
HZWE
1
is less than t
and WE signals must be LOW and CE
62128V25-100
Min.
100
100
100
100
10
10
10
90
60
10
0
0
0
0
LZWE
Max.
100
100
100
75
50
50
50
CY62128V Family
for any given device.
62128V18-200
Min.
200
200
190
190
125
100
10
10
10
15
0
0
0
0
2
Max.
HIGH to initiate a
200
200
125
200
100
75
75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns