GAL20VP8B-15LP LATTICE [Lattice Semiconductor], GAL20VP8B-15LP Datasheet - Page 11
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GAL20VP8B-15LP
Manufacturer Part Number
GAL20VP8B-15LP
Description
High-Speed E2CMOS PLD Generic Array Logic
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.GAL20VP8B-15LP.pdf
(17 pages)
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
*Characterized but not 100% tested.
PARAMETER
AC Switching Characteristics
Capacitance (T
SYMBOL
f
max
t
t
t
t
t
t
t
t
t
wh
dis
pd
co
cf
su
en
wl
h
C
C
2
I/O
I
3
COND
TEST
—
—
—
—
—
C
A
A
A
A
A
B
B
C
1
.
A
= 25 C, f = 1.0 MHz)
Input or I/O to Combinational Output
Clock to Output Delay
Clock to Feedback Delay
Setup Time, Input or Feedback before Clock
Hold Time, Input or Feedback after Clock
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
Maximum Clock Frequency with
No Feedback
Clock Pulse Duration, High
Clock Pulse Duration, Low
Input or I/O to Output Enabled
OE to Output Enabled
Input or I/O to Output Disabled
OE to Output Disabled
DESCRIPTION
Input Capacitance
I/O Capacitance
PARAMETER
Over Recommended Operating Conditions
MAXIMUM*
10
15
11
Specifications GAL20VP8
UNITS
pF
pF
55.5
MIN. MAX.
80
80
—
—
—
—
—
3
2
8
0
6
6
COM
-15
V
4.5
15
10
15
12
15
12
TEST CONDITIONS
—
—
—
—
—
—
—
V
CC
CC
= 5.0V, V
= 5.0V, V
MIN. MAX.
10
40
50
50
10
10
—
—
—
—
—
3
2
0
COM
-25
I/O
I
= 2.0V
= 2.0V
25
15
10
20
15
20
15
—
—
—
—
—
—
—
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns