A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 96

• Manufacturer Part Number: A3PE1500-1FG896
• Description: ProASIC3E Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ProASIC3E DC and Switching Characteristics
2 -8 4
Previous Version
Advance v0.6
(continued)
Advance v0.4
(October 2005)
Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
The "V
The "V
The "GL Globals" section was updated to include information about direct
input into quadrant clocks.
V
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
V
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured
on quiet I/Os).
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
Table 3-5 • Package Thermal Resistivities was updated.
Table 3-10 • Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
t
3-95 • RAM512X18.
The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
Figure 3-43 • Write Access After Write onto Same Address, Figure
3-44 • Read Access After Write onto Same Address, and Figure 3-45 • Write
Access After Read onto Same Address are new.
Figure 3-53 • Timing Diagram was updated.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
The Delay Increments in the Programmable Delay Blocks specification in
Figure 2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
The "Introduction" of the "Introduction" section was updated.
WRO
JTAG
PUMP
was deleted from the "TCK Test Clock" section.
programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
CCPLF
PUMP
and t
PLL Supply Voltage" section was updated.
Programming Supply Voltage" section was updated.
CCKH
were added to Table 3-94 • RAM4K9 and Table
Changes in Current Version (v1.2)
v1.2
3-74 to
3-71 to
Page
2-64
2-40
2-50
2-50
2-51
2-51
2-51
3-74
3-23
3-73
3-80
2-28
2-24
2-21
2-25
2-25
2-25
2-27
2-28
N/A
N/A
3-2
3-2
3-5
3-5
3-5
3-8
2-8