STM32F103C4H6ATR STMICROELECTRONICS [STMicroelectronics], STM32F103C4H6ATR Datasheet - Page 11

• Manufacturer Part Number: STM32F103C4H6ATR
• Description: Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 2.
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
64 MHz.
48 MHz or 72 MHz.
OSC32_OUT
OSC32_IN
OSC_OUT
OSC_IN
MCO
Clock tree
32.768 kHz
4-16 MHz
HSE OSC
Main
Clock Output
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
PLLXTPRE
PLL
/2
/128
LSE
/2
Doc ID 15060 Rev 3
LSI
RTCSEL[1:0]
/2
HSE
PLLCLK
SYSCLK
HSI
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
72 MHz
to RTC
max
IWDGCLK
Prescaler
/1, 2..512
AHB
Prescaler
/1, 1.5
USB
TIM1 timer
If (APB2 prescaler =1) x1
else
/1, 2, 4, 8, 16
/1, 2, 4, 8, 16
TIM2, TIM3
If (APB1 prescaler =1) x1
else
/8
Prescaler
Prescaler
72 MHz max
APB1
APB2
Prescaler
/2, 4, 6, 8
Clock
Enable (3 bits)
ADC
48 MHz
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
72 MHz max
36 MHz max
ADCCLK
Peripheral Clock
Peripheral Clock
Enable (13 bits)
Enable (11 bits)
x2
USBCLK
to USB interface
x2
HCLK
to AHB bus, core,
memory and DMA
FCLK Cortex
free running clock
to Cortex System timer
Peripheral Clock
Enable (1 bit)
Peripheral Clock
Enable (3 bits)
TIM1CLK
TIMXCLK
PCLK1
PCLK2
to APB1
peripherals
to APB2
peripherals
to TIM2, TIM3
to ADC
to TIM1
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