ATMEGA48V_09 ATMEL [ATMEL Corporation], ATMEGA48V_09 Datasheet - Page 116
ATMEGA48V_09
Manufacturer Part Number
ATMEGA48V_09
Description
8-bit Microcontroller with 8K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA48V_09.pdf
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116
Output Compare Units
ATmega48/88/168
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 Flag is not required (if an interrupt handler is used).
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-
pare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 15-4
bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 15-4. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
shows a block diagram of the Output Compare unit. The small “n” in the register and
OCRnxH Buf. (8-bit)
(See “Modes of Operation” on page
OCRnxH (8-bit)
BOTTOM
OCRnx Buffer (16-bit Register)
TEMP (8-bit)
TOP
OCRnx (16-bit Register)
OCRnxL Buf. (8-bit)
OCRnxL (8-bit)
DATA BUS
Waveform Generator
WGMn3:0
=
(16-bit Comparator )
(8-bit)
COMnx1:0
TCNTnH (8-bit)
OCFnx (Int.Req.)
119.)
TCNTn (16-bit Counter)
TCNTnL (8-bit)
2545R–AVR–07/09
OCnx
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