MC35XS3400 FREESCALE [Freescale Semiconductor, Inc], MC35XS3400 Datasheet - Page 30

• Manufacturer Part Number: MC35XS3400
• Description: Quad High Side Switch (Quad 35m?)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

on the CSNS pin for the corresponding output. The default
value [0] is the low ratio
ADDRESS A
REGISTER (OCR)
corresponding output over-current protection through the
SPI. Each output “s” is independently selected for
configuration based on the state of the D14 : D13 bits
(Table
curve and D[5:4] bits inrush curve for selected output, as
shown
.
replaced by OCHI2 during t
30
35XS3400
Table 14. Current Sense Ratio Selection
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 15. Cooling and Inrush Curve Selection
Table 16. Inrush Curve Selection
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio
The OCR_s register allows the MCU to configure
D[7:6] bits allow to MCU to programmable bulb cooling
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is
BC1_s (D7)
OC1_s (D5)
CSNS_high_s (D0)
Table 15
11).
0
0
1
1
0
0
1
1
0
1
1
A
and
0
100 — OUTPUT OVER-CURRENT
Table
BC0_s (D6)
OC0_s (D4)
(Table
16.
0
1
0
1
OC1
0
1
0
1
, as shown
14).
Current Sense Ratio
Profile Curves Speed
CRS0 (default)
Profile Curves Speed
medium (default)
CRS1
Figure
slow (default)
medium
very slow
medium
slow
fast
fast
13.
current levels in steady state, as defined in
mode, as described
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
through the SPI.
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe mode for V
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
reference by PWM module, as described in the following
Table
Table 18. Over-current Mode Selection
OC_mode_s (D0)
I
I
I
I
I
I
I
I
I
I
Figure 13. Over-current profile with OCHI bit set to ‘1’
OCH
OCH2
OC1
OC2
OC3
OC4
OCLO4
OCLO3
OCLO2
OCLO1
Table 17. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1)
The wire harness is protected by one of four possible
Bit D0 (OC_mode_sel) allows to select the over-current
The GCR register allows the MCU to configure the device
Bit D8 allows the MCU to enable or disable the V
Bit D7 allows the MCU to enable or disable the PWM
Bit D6 (CLOCK_sel) allows to select the clock used as
1
19.
t
OC1
0
0
1
1
0
1
t
OC2
t
OC3
t
OC4
inrush current and bulb cooling management
0
1
0
1
Table
only inrush current management (default)
Analog Integrated Circuit Device Data
DD
t
OC5
< V
18.
DD(FAIL).
Over-current Mode
t
OC6
Steady State Current
Freescale Semiconductor
OCLO2 (default)
OCLO3
OCLO4
OCLO1
t
OC7
Table
17.
Time
DD
failure