ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 80

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

ADP1053
Table 131. Register 0xFEC1—Flag Register 2 and Register 0xFEC6—Latched Flag Register 2 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Table 132. Register 0xFEC2—Flag Register 3 and Register 0xFEC7—Latched Flag Register 3 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Table 133. Register 0xFEC3—Flag Register 4 and Register 0xFEC8—Latched Flag Register 4 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Bit Name
POWER_SUPPLY_B
PGOOD_B
CS1_B_OCP
CS2_B_OCP
UVP_B
OVP_B
LIGHTLOAD_B
VS_SET_ERR_B
Bit Name
Reserved
VDD_OV
CS_OCP
OTP2
OTP1
ACSNS
EEPROM_CRC
FLAGIN
Bit Name
Reserved
POWER_SUPPLY_C
FLAGOUT
EEPROM_UNLOCKED
SOFTSTART_FILTER_B
SOFTSTART_FILTER_A
MODULATION_B
MODULATION_A
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
Description
Channel B power supply is off and the PWM outputs are disabled.
This bit stays high until PSON_B is asserted.
Power-good fault on Channel B. This flag is set when the UVP_B,
POWER_SUPPLY_B, EEPROM_CRC, or SOFTSTART_FILTER_B flag
is set. The ACSNS and OTW2 flags can also be programmed to be
included.
The voltage at CS1_B is above the 1.2 V threshold.
The voltage at CS2_B is above its threshold.
VS_B is below its threshold.
OVP_B is above its threshold.
Channel B is in light load mode (CS2_B current is below the light
load threshold).
The intended VS_B reference setting is outside the allowed range.
Description
Reserved.
Overvoltage condition (V
remains functional, but a PSON toggle is required to restart
the power supply.
The voltage at CS is above the 1.2 V threshold.
Temperature of Zone 2 is above the OTP2 threshold.
Temperature of Zone 1 is above the OTP1 threshold.
ACSNS is below its threshold.
The downloaded EEPROM contents are incorrect.
The external flag pin (FLGI/SYNI) is set.
Description
Reserved.
Channel C power supply is off and the PWM outputs are disabled.
This bit stays high until PSON_C is asserted.
The FLGO/SYNO pin is set in response to the LIGHTLOAD_A or
LIGHTLOAD_B flag.
The EEPROM is unlocked.
Channel B soft start filter is in use.
Channel A soft start filter is in use.
Channel B digital filter is at its minimum or maximum limit.
Channel A digital filter is at its minimum or maximum limit.
Rev. A | Page 80 of 84
DD
is above limit). The I
2
C interface
Register
0xFE09,
0xFE78,
0xFE8A
0xFE00,
0xFE71
0xFE01,
0xFE19
0xFE03,
0xFE29
0xFE02,
0xFE27
0xFE1B,
0xFE6A
0xFE1F,
0xFE21
Register
0xFE06
0xFE04,
0xFE6F
0xFE05,
0xFE76
0xFE05,
0xFE75
0xFE04,
0xFE78
0xFE06,
0xFE0F
Register
0xFE0F
0xFE3F
0xFE3E
0xFE3D
0xFE3C
Data Sheet
Action
None
PGOOD_B pin
set low
Programmable
Programmable
Programmable
Programmable
Programmable
None
Action
Programmable
Programmable
Programmable
Programmable
Programmable
Immediate
shutdown
Programmable
Action
None
None
None
None
None
None
None