ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 63

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
Table 83. Register 0xFE3D—Channel B Modulation Limit
Bits
[7:0]
Table 84. Register 0xFE3E—Channel A Feedforward and Soft Start Digital Filter Setting
Bits
[7:6]
5
4
3
2
[1:0]
Table 85. Register 0xFE3F—Channel B Feedforward and Soft Start Digital Filter Setting
Bits
[7:6]
5
4
3
2
[1:0]
Bit Name
Channel B
modulation limit
Bit Name
Reserved
High frequency ADC
debounce time
High frequency ADC
debounce enable
Feedforward ADC
selection
Feedforward enable
Soft start filter gain
Bit Name
Reserved
High frequency ADC
debounce time
High frequency ADC
debounce enable
Feedforward ADC
selection
Feedforward enable
Soft start filter gain
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register sets the maximum duty cycle modulation limit for PWM outputs in Channel B.
The modulation limit is the maximum time variation for the modulated edges from the default
timing (see Figure 42). The step size of an LSB depends on the switching frequency.
Switching Frequency
48.8 kHz to 86.8 kHz
97.7 kHz to 183.8 kHz
195.3 kHz to 378.8 kHz
390.6 kHz to 625.0 kHz
Description
Reserved.
This bit sets the debounce time for detecting the settling of the VS_A high frequency ADC.
Bit 4 must be set to 1.
0 = 5 ms.
1 = 10 ms.
Setting this bit enables a debounce time for detecting the settling of the VS_A high frequency
ADC at the end of a soft start. The debounce time is set using Bit 5.
This bit should be set to 1 (factory default setting). This bit selects the 11-bit ACSNS ADC for
feedforward control of Channel A. Do not set this bit to 0.
This bit enables or disables feedforward control on Channel A.
0 = feedforward control disabled on Channel A.
1 = feedforward control enabled on Channel A.
These bits set the low-pass filter gain for Channel A during soft start.
Bit 1
0
0
1
1
Description
Reserved.
This bit sets the debounce time for detecting the settling of the VS_B high frequency ADC.
Bit 4 must be set to 1.
0 = 5 ms.
1 = 10 ms.
Setting this bit enables a debounce time for detecting the settling of the VS_B high frequency
ADC at the end of a soft start. The debounce time is set using Bit 5.
This bit should be set to 1 (factory default setting). This bit selects the 11-bit ACSNS ADC for
feedforward control of Channel B. Do not set this bit to 0.
This bit enables or disables feedforward control on Channel B.
0 = feedforward control disabled on Channel B.
1 = feedforward control enabled on Channel B.
These bits set the low-pass filter gain for Channel B during soft start.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Bit 0
0
1
0
1
Rev. A | Page 63 of 84
Soft Start Filter Gain
1
2
4
8
Soft Start Filter Gain
1
2
4
8
LSB Step Size
80 ns
40 ns
20 ns
10 ns
ADP1053