ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 57

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
Register 0xFE18 sets the CS2_A OCP threshold, and Register 0xFE19 sets the CS2_B OCP threshold.
Table 48. Register 0xFE18 and Register 0xFE19—CS2_A OCP Threshold and CS2_B OCP Threshold
Bits
[7:0]
Register 0xFE1A selects the CS2_A high-side/low-side setting, sets the CS2_A_OCP flag debounce time, and sets the light load threshold
for Channel A. Register 0xFE1B sets the same values for Channel B.
Table 49. Register 0xFE1A and Register 0xFE1B—CS2_A/CS2_B High-Side/Low-Side Setting and Channel A/Channel B Light Load
Threshold
Bits
7
[6:5]
4
[3:0]
CHANNEL A/CHANNEL B VOLTAGE SENSE AND LIMIT SETTING REGISTERS
Table 50. Register 0xFE1C—VS_A Gain Trim
Bits
7
[6:0]
Table 51. Register 0xFE1D—VS_B Gain Trim
Bits
7
[6:0]
Bit Name
CS2_A/CS2_B OCP
threshold
Bit Name
High-side/low-side
sensing
CS2_A_OCP/CS2_B_
OCP flag debounce
LIGHTLOAD_A/
LIGHTLOAD_B flag
blanking in soft start
CS2_A/CS2_B light
load threshold
Bit Name
Trim polarity
VS_A gain trim
Bit Name
Trim polarity
VS_B gain trim
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
The 8-bit OCP threshold set in this register is compared with Bits[15:8] in the CS2_A or CS2_B
value register (Register 0xFED3 or Register 0xFED4). If the eight MSBs in the value register are
higher, the CS2_A_OCP or CS2_B_OCP flag is set. When the OCP threshold is set to 0xFF (255
decimal), the CS2_A_OCP or CS2_B_OCP flag is always cleared. The range of the CS2 ADC is
0 mV to 120 mV, so the step size is 120 mV/4096 = 29.3 μV. Therefore, the threshold step size
is 29.3 μV × 16 = 468.8 μV. The OCP threshold can be calculated as follows:
Threshold Target (V) = (Threshold Code + 1) × 468.8 μV
The GUI converts the voltage to current based on the value of the current sensing resistor.
The valid range of the register code is from 2 to 241 decimal.
Description
This bit configures the part for high-side resistor current sensing or low-side current sensing.
0 = CS2_A or CS2_B is configured for low-side sensing.
1 = CS2_A or CS2_B is configured for high-side sensing.
These bits set the CS2_A_OCP/CS2_B_OCP flag debounce time.
Bit 6
0
0
1
1
This bit specifies whether to blank the LIGHTLOAD_A/LIGHTLOAD_B flag during soft start.
0 = do not blank the LIGHTLOAD_A/LIGHTLOAD_B flag during Channel A/Channel B soft start.
1 = blank the LIGHTLOAD_A/LIGHTLOAD_B flag during Channel A/Channel B soft start.
These bits set the CS2_A/CS2_B ADC light load threshold value, below which the LIGHTLOAD_A or
LIGHTLOAD_B flag is set and Channel A or Channel B enters light load mode. Each LSB corresponds
to 64 LSBs of the 12-bit CS2_A/CS2_B reading, which is 1.56% of the full range (1.875 mV). Hysteresis
is included to exit light load mode; the threshold to exit light load mode is 96 LSBs greater than
the threshold to enter light load mode (96 LSBs = 2.34% of the full range, that is, 2.8125 mV).
When these bits are set to 0, the LIGHTLOAD_A/LIGHTLOAD_B flag is always cleared.
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
These bits set the amount of gain trim that is applied to the VS_A ADC reading. This register
trims the voltage at the VS_A pin for external resistor tolerances. For more information, see the
VS_A and VS_B Gain Trim section.
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
These bits set the amount of gain trim that is applied to the VS_B ADC reading. This register
trims the voltage at the VS_B pin for external resistor tolerances. For more information, see the
VS_A and VS_B Gain Trim section.
Bit 5
0
1
0
1
Rev. A | Page 57 of 84
Typical Debounce Time
0 ms
20 ms
200 ms
1 sec
ADP1053