ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 51

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
Table 32. Register 0xFE06—Flag Reenable Delay, VDD_OV, and FLAGIN Configuration
Bits
[7:6]
5
4
[3:2]
[1:0]
Register 0xFE07 selects flags to be blanked during soft start. When a flag is blanked, the flag is set but no action takes place. During the soft
start of any channel, the following flags are always blanked: FLAGIN, OTP1, OTP2, and ACSNS. During the soft start of Channel A, these
flags are also blanked: REVERSE_A and UVP_A. During the soft start of Channel B, these flags are also blanked: REVERSE_B and UVP_B.
Table 33. Register 0xFE07—Flag Blanking During Soft Start
Bits
7
6
5
4
3
2
1
0
Bit Name
Flag reenable delay
VDD_OV flag ignore
VDD_OV flag
debounce
FLAGIN action
Action after FLAGIN
is cleared
Bit Name
Reserved
CS_OCP blanking
OVP_B blanking
OVP_A blanking
CS2_B_OCP blanking
CS2_A_OCP blanking
CS1_B_OCP blanking
CS1_A_OCP blanking
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
0 = blank CS_OCP flag during Channel C soft start.
1 = do not blank CS_OCP flag.
0 = blank OVP_B flag during Channel B soft start.
1 = do not blank OVP_B flag.
0 = blank OVP_A flag during Channel A soft start.
1 = do not blank OVP_A flag.
0 = blank CS2_B_OCP flag during Channel B soft start.
1 = do not blank CS2_B_OCP flag.
0 = blank CS2_A_OCP flag during Channel A soft start.
1 = do not blank CS2_A_OCP flag.
0 = blank CS1_B_OCP flag during Channel B soft start.
1 = do not blank CS1_B_OCP flag.
0 = blank CS1_A_OCP flag during Channel A soft start.
1 = do not blank CS1_A_OCP flag.
Description
These bits specify the global delay from when a flag is cleared to the soft start process.
Bit 7
0
0
1
1
This bit enables or disables the VDD_OV flag.
0 = VDD_OV flag enabled. When there is a VDD overvoltage condition, the flag is set and the
part shuts down. When the flag is cleared, the part restarts.
1 = VDD_OV flag is always cleared.
This bit sets the debounce time for the VDD_OV flag.
0 = 500 μs debounce time.
1 = 2 μs debounce time.
These bits specify the action to take when the FLAGIN flag is set.
Bit 3
0
0
1
1
These bits specify the action to take after the FLAGIN flag is cleared.
Bit 1
0
0
1
1
Bit 6
0
1
0
1
Bit 2
0
1
0
1
Bit 0
0
1
0
1
Rev. A | Page 51 of 84
Typical Delay Time
250 ms
500 ms
1 sec
2 sec
FLAGIN Action
None
Disable PWM outputs in Channel A
Disable PWM outputs in Channel B
Disable all PWM outputs (Channel A, Channel B, and Channel C)
Action After FLAGIN Is Cleared
After the reenable delay time, the PWM outputs are reenabled using the soft
start process
The PWM outputs are reenabled immediately without a soft start
A PSON signal is needed to reenable the PWM outputs
A PSON signal is needed to reenable the PWM outputs
ADP1053