ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 10

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

ADP1053
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mnemonic
VS+_A
VS−_A
PGND_A
OVP_A
CS2−_A
CS2+_A
PGOOD_A
CS1_A
ACSNS
PSON_A
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
Description
Noninverting Input of the Voltage Sense ADC for Channel A Loop Control. This signal is referenced to VS−_A.
Inverting Input of the Voltage Sense ADC for Channel A Loop Control. There should be a low ohmic connection
to AGND.
Reference Pin for Channel A Overvoltage Protection (OVP_A).
Overvoltage Protection Comparator Input for Channel A. This signal is referenced to PGND_A.
Inverting Input of the Differential Current Sense ADC for Channel A. The nominal voltage at this pin should be
1 V for optimal operation.
Noninverting Input of the Differential Current Sense ADC for Channel A. The nominal voltage at this pin should
be 1 V for optimal operation.
Power-Good Output (Open-Drain) for Channel A. This signal is referenced to AGND. This pin is controlled by the
PGOOD_A flag and is driven low when the flag is set. The PGOOD_A flag is set when the POWER_SUPPLY_A, UVP_A,
EEPROM_CRC, or SOFTSTART_FILTER_A flag is set. The ACSNS and OTW1 flags can also be programmed to be included.
CS1 ADC Input and Fast Current Sense Input for Channel A. This signal is referenced to AGND.
AC Sense ADC and Feedforward Operation Input. This pin is connected upstream of the main inductor through a
resistor divider network. The nominal voltage at this pin should be 1 V. This signal is referenced to AGND.
Power Supply On Input for Channel A. This signal is referenced to AGND.
OUT1 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT2 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT3 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT4 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT5 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT6 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT7 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
OUT8 PWM Logic Output Drive. This pin is connected to the input of a FET driver; it can be disabled when not in
use. This signal is referenced to AGND.
PGOOD_A
NOTES
1. THE EXPOSED PAD ON THE UNDERSIDE OF THE
PGND_A
PSON_A
PACKAGE SHOULD BE SOLDERED TO AGND.
CS2–_A
CS2+_A
ACSNS
OVP_A
VS+_A
CS1_A
VS–_A
10
1
2
3
4
5
6
7
8
9
Figure 4. Pin Configuration
Rev. A | Page 10 of 84
(Not to Scale)
ADP1053
TOP VIEW
30
29
28
27
26
25
24
23
22
21
VS+_B
VS–_B
PGND_B
OVP_B
CS2–_B
CS2+_B
PGOOD_B
CS1_B
CS
PSON_B
Data Sheet