HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 47

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) New units, ‘
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
9) Input clock jitter spec parameter. These parameters and the ones in
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Parameter
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command
period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
under operation. Unit ‘
DDR2–533, ‘
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
– 272 ps and
t
= - 900 ps – 293 ps = – 1193 ps and
these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
DQSCK.MAX(DERATED)
DDQ
= 1.8 V ± 0.1V;
t
CK.AVG
t
CK
t
ERR(6- 10PER).MAX
‘ is used for both concepts. Example:
‘ and ‘
=
t
V
DQSCK.MAX
n
DD
CK
n
= 1.8 V ± 0.1 V.
CK
‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
= + 293 ps, then
–
t
ERR(6-10PER).MIN
t
LZ.DQ.MAX(DERATED)
V
REF
V
stabilizes. During the period before
TT
t
.
DQSCK.MIN(DERATED)
= 400 ps + 272 ps = + 672 ps. Similarly,
t
t
CK.AVG
XP
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
MRD
OIT
QH
QHS
REFI
RFC
RP
RPRE
RPST
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
= 2 [
+
n
t
CK
ERR.2PER(Min)
] means; if Power Down exit is registered at Tm, an Active command may
47
=
t
Chapter 7.3
DQSCK.MIN
DDR2–667
2
0
t
—
—
—
105
t
0.9
0.4
7.5
0.35
0.4
15
7.5
2
7 – AL
2
t
200
RL–1
Min.
HP
RP
RFC
.
–
+10
–
t
QHS
t
ERR(6-10PER).MAX
V
are referred to as 'input clock jitter spec parameters' and
t
REF
CK.AVG
512-Mbit Double-Data-Rate-Two SDRAM
stabilizes, CKE = 0.2 x
‘ represents the actual
t
LZ.DQ
Max.
—
12
—
340
7.8
3.9
—
—
1.1
0.6
—
—
0.6
—
—
—
—
—
—
—
for DDR2–667 derates to
= – 400 ps – 293 ps = – 693 ps and
HYB18T512[40/80/16]0B[C/F]
t
ERR(6-10per)
V
Unit
n
ns
ps
ps
µs
µs
ns
ns
t
t
ns
t
t
ns
ns
n
n
n
ns
n
n
CK.AVG
CK.AVG
CK.AVG
CK.AVG
DDQ
CK
CK
CK
CK
CK
CK
t
of the input clock. (output
CK.AVG
Internet Data Sheet
is recognized as low.
t
ERR(6-10PER).MIN
of the input clock
Note
1)2)3)4)5)6)7)
34)
25)
26)
27)28)
28)29)
30)
31)32)
31)33)
34)
34)
34)35)
34)
t
LZ.DQ.MIN(DERATED)
=