HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 46

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support
35)
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Parameter
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated DQ signals
DQS latching rising transition to associated clock
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
Data-out high-impedance time from CK / CK
Address and control input hold time
Control & address input pulse width for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
t
nRP
WTR
t
JIT.DUTY.MAX
t
= RU{
is at lease two clocks (2 x
JIT.DUTY.MAX
t
RP
/
= 0.6 x
t
CK.AVG
= + 93 ps, then
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
t
t
RPST.MIN(DERATED)
CK
) independent of operation frequency.
DRAM Component Timing Parameter by Speed Grade - DDR2–667
=
t
RPST.MIN
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DSH
DSS
HP
HZ
IH.BASE
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
+
t
JIT.DUTY.MIN
46
= 0.4 x
DDR2–667
–450
2
0.48
3000
3
0.48
WR +
t
t
175
0.35
–400
0.35
0.35
—
–0.25
100
0.2
0.2
Min(
t
—
275
0.6
200
2 ×
t
0
Min.
IS
IH
CL.ABS
AC.MIN
+
t
t
AC.MIN
t
CK .AVG
CH.ABS
t
)
CK.AVG
t
nRP
,
512-Mbit Double-Data-Rate-Two SDRAM
– 72 ps = + 928 ps and
+
t
nPARAM
Max.
+450
—
0.52
8000
—
0.52
—
—
—
—
+400
—
—
240
+0.25
—
—
—
—
t
—
—
—
t
t
12
AC.MAX
AC.MAX
AC.MAX
= RU{
HYB18T512[40/80/16]0B[C/F]
t
JIT.DUTY
t
t
nRP
RP
t
PARAM
= 15 ns, the device will support
= RU{
of the input clock. (output
t
RPST.MAX(DERATED)
Unit
ps
n
t
ps
n
t
n
ns
ps
t
ps
t
t
ps
t
ps
t
t
ps
ps
ps
t
ps
ps
ps
ns
/
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK
CK
CK
t
CK.AVG
t
Internet Data Sheet
RP
/
t
JIT.DUTY.MIN
t
TABLE 48
CK.AVG
}, which is in clock
Note
1)2)3)4)5)6)7)
8)
9)10)
11)
9)10)
12)13)
18)19)14)
8)
15)
16)
17)18)19)
16)
16)
20)
8)21)
24)22)
23)24)
8)21)
8)21)
34)
}, which is in
=
= – 72 ps
t
RPST.MAX