93C46A-E/MC MICROCHIP [Microchip Technology], 93C46A-E/MC Datasheet - Page 11
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93C46A-E/MC
Manufacturer Part Number
93C46A-E/MC
Description
1K Microwire Compatible Serial EEPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.93C46A-EMC.pdf
(28 pages)
2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
FIGURE 2-10:
FIGURE 2-11:
© 2005 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
CS
V
DI
DI
CC
must be
Write All (WRAL)
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
4.5V for proper operation of WRAL.
1
1
High-Z
High-Z
WRAL TIMING FOR 93AA AND 93LC DEVICES
WRAL TIMING FOR 93C DEVICES
0
0
0
0
0
0
1
1
x
x
•••
•••
x
x
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
Dx
CC
Note:
must be
CSL
•••
•••
).
D0
D0
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
4.5V for proper operation of WRAL.
T
T
CSL
CSL
T
WL
T
WL
Busy
Busy
T
T
SV
SV
Ready
Ready
H
H
DS21749F-page 11
IGH
IGH
T
T
-Z
-Z
CZ
CZ