EL5325 INTERSIL [Intersil Corporation], EL5325 Datasheet
EL5325
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EL5325 Summary of contents
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... The EL5325 has 12 outputs and is available in a 28-pin TSSOP package. They are specified for operation over the full -40°C to +85°C temperature range. Ordering Information PART TAPE & ...
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... Duty Cycle Duty Cycle for EXT_OSC Signal INL Integral Nonlinearity Error DNL Differential Nonlinearity Error F_OSC Internal Refresh Oscillator Frequency 2 EL5325 = 25°C) Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C and 7V (max) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C S Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85° ...
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... OUTB 28 OUTA 15 OUTL 16 OUTK 18, 25 GND 3 EL5325 PIN TYPE Logic Input Chip select, low enables data input to logic Logic Input Serial data input Logic Input Serial data clock Logic Output Serial data output Logic Input/Output External oscillator input or internal oscillator output ...
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... C =180pF L FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING) M=400µs/DIV 10V 5V OUTPUT 0V FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V) 4 EL5325 =2V REFL 810 1010 5mA/DIV C =4.7nF L R =20Ω S 200mV/DIV FIGURE 4. TRANSIENT LOAD REGULATION (SINKING) SCLK SDA FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V REFH=13V, REFL=2V 1 ...
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... Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5325. As all of the output buffers are identical also possible to use the EL5325 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy ...
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... Data appears on the SDO pin at the 16th falling SCLK edge after being applied to the SDI pin. To control the multiple EL5325 chips from a single three-wire serial port, just connect the ENA pins and the SCLK pins together, connect the SDO pin to the SDI pin on the next chip ...
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... CLOCK OSCILLATOR The EL5325 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn’t be changed ) - V REFL at the rising edges of the OSC clock ...
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... This means that a large change of 16V can take between 4.6ms to 5.2ms depending on the absolute timing relative to the update cycle. 8 EL5325 EIGHT VOLTAGE CHANNEL SOURCES MEMORY ...
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... Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5325. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5325 should be connected to the analog ground plane ...
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... OUTF CAP 0.1µF OUTK REFL GND OUTL EL5325 MIDDLE REFERENCE REFH OUTA OSC +12V VS OUTB 0.1µF OUTC +5V VSD 0.1µF OUTD SDI SCK OUTE ENA CAP 0.1µF OUTF LOW REFERENCE VOLTAGE REFL 0.1µF OUTK GND OUTL EL5325 COLUMN (SOURCE) DRIVER LCD PANEL ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 EL5325 ...