SSTUB32866EC/G PHILIPS [NXP Semiconductors], SSTUB32866EC/G Datasheet
SSTUB32866EC/G
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SSTUB32866EC/G Summary of contents
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SSTUB32866 1.8 V 25-bit 14-bit configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 9 October 2006 1. General description The SSTUB32866 is a 1.8 V configurable register specifically designed ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Solder process SSTUB32866EC/G Pb-free (SnAgCu solder ball compound) SSTUB32866EC/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUB32866EC/G SSTUB32866EC/S SSTUB32866_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity ...
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NXP Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUB32866 Register A configuration with and SSTUB32866_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with ...
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NXP Semiconductors RESET CK CK D2, D3, D5, D6 D14 VREF C1 PAR_IN C0 Fig 2. Parity logic diagram for Register A configuration (positive logic SSTUB32866_2 Product data ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for LFBGA96 Fig 4. Ball mapping register ( SSTUB32866_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity SSTUB32866EC/G SSTUB32866EC/S ball A1 index area ...
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NXP Semiconductors Fig 5. Ball mapping Register A ( Fig 6. Ball mapping Register B ( SSTUB32866_2 Product data sheet 1.8 V DDR2-800 configurable ...
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NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3 A4, C3, C4, E3, E4, DD G3, G4, J3, J4, L3, L4, N3, ...
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NXP Semiconductors [3] Data outputs = Q2, Q3, Q5, Q6 Q25 when and Data outputs = Q2, Q3, Q5, Q6 Q14 when and Data ...
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NXP Semiconductors The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either ...
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NXP Semiconductors Table 5. Parity and standby function table L = LOW voltage level HIGH voltage level don’t care; RESET DCS CSR ...
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... PAR_IN inputs data (Dn), CSR, and V ref PAR_IN inputs data (Dn), CSR, and - PAR_IN inputs [1] RESET, Cn 0.65 [1] RESET [2] CK, CK 0.675 [2] CK, CK 600 - - operating in free air SSTUB32866EC/G 0 SSTUB32866EC/S 0 Rev. 02 — 9 October 2006 SSTUB32866 Typ Max - 2.0 V 0. 0.040 0.040 ref ref ...
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NXP Semiconductors 10. Characteristics Table 8. Characteristics At recommended operating conditions (see Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current per DDD MHz C ...
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NXP Semiconductors Table 9. Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t setup time su t hold time ...
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NXP Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUB32866 used as a single device SSTUB32866_2 ...
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NXP Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUB32866 ( Register A configuration) device used in pair; C0 ...
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NXP Semiconductors RESET DCS CSR D14 Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUB32866 device. Fig 9. Timing diagram for the second ...
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NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at ...
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NXP Semiconductors Fig 13. Voltage waveforms; setup and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) SSTUB32866_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer ...
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NXP Semiconductors 11.2 Data output slew rate measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. ...
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NXP Semiconductors 11.3 Error output load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 20. Load circuit, error output measurements ...
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NXP Semiconductors Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to 11.4 Partial parity out load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: ...
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NXP Semiconductors Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to SSTUB32866_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity LVCMOS RESET output and t are ...
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NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ...
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NXP Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not ...
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NXP Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...
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NXP Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...
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... Legal texts have been adapted to the new company name where appropriate. • Table 1 “Ordering • added • Figure 3 “Pin configuration for LFBGA96” • Table 7 “Recommended operating SSTUB32866EC/G and SSTUB32866EC/S • Table 9 “Timing “See Section • Table 10 “Switching – changed parameter description of t – changed parameter description of t “ ...
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NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...