ISL6322_07 INTERSIL [Intersil Corporation], ISL6322_07 Datasheet
ISL6322_07
Related parts for ISL6322_07
ISL6322_07 Summary of contents
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Data Sheet Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I Interface for Intel VR10, VR11, and AMD Applications The ISL6322 four-phase PWM control IC provides a precision voltage regulation system for advanced microprocessors. The integration of power ...
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Ordering Information PART NUMBER PART TEMP. (Note) MARKING (°C) ISL6322CRZ* ISL6322 CRZ 7x7 QFN ISL6322IRZ* ISL6322 IRZ - 7x7 QFN *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus ...
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Block Diagram OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC SS/RST/ SCL LOGIC SDA MODE/DAC VRSEL SELECT VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 REF FB COMP ...
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ISL6322 Integrated Driver Block Diagram DRSEL PWM SOFT-START AND FAULT LOGIC 2 Simplified I C Bus Architecture SCL SDA SCL SLAVE SLAVE ISL6322 ISL6322 SHOOT- GATE CONTROL THROUGH LOGIC PROTECTION SDA BUS ...
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Typical Application - ISL6322 (4-Phase) FB IDROOP VDIFF COMP VSEN RGND +5V VCC OFS FS REF SCL SDA SS / RST / A0 ISL6322 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD +12V EN GND 5 ISL6322 ISL6322 ...
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Typical Application - ISL6322 with NTC Thermal Compensation (4-Phase) FB IDROOP COMP VSEN RGND +5V VCC OFS FS REF SCL SDA SS / RST / A0 ISL6322 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD +12V EN GND ...
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Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER REFERENCE AND DAC System Accuracy (1.000V to 1.600V) System Accuracy (0.600V to 1.000V) System Accuracy (0.375V - 0.600V) DAC Input Low Voltage (VR10, VR11) DAC Input High Voltage (VR10, VR11) ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER Overvoltage Hysteresis SWITCHING TIME (Note 3) UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-On Non-Overlap LGATE Turn-On Non-Overlap GATE DRIVE RESISTANCE (Note 3) Upper ...
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Functional Pin Description VCC VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1μF ceramic capacitor. PVCC1_2 and PVCC3 These pins are the power supply pins for ...
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PHASE1, PHASE2, and PHASE3 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the upper MOSFET drives. LGATE1, LGATE2, and LGATE3 These pins are used to control the lower MOSFETs. Connect ...
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PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the DC components of the inductor currents combine to feed the load. To understand the ...
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Channel-Current Balance One important benefit of multiphase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of ...
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L ------------- + 1 ⎝ ⎠ DCR ⋅ ⋅ ------------------------------------------------------- - K DCR ⋅ ) ⎛ ⎞ ⋅ ⋅ ⎜ ⎟ s ----------------------- - ...
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TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 VID0 VID5 ...
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TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 VID0 VID5 ...
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TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 ...
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Voltage Regulation The integrating compensation network shown in Figure 6 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current ...
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Output-Voltage Offset Programming The ISL6322 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R is connected between OFS OFS and VCC, the voltage across it is regulated to ...
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AMD Dynamic VID Transitions When running in AMD 5-bit or 6-bit modes of operation, the ISL6322 responds differently to a dynamic VID change than when in Intel VR10 or VR11 mode. In the AMD modes, the ISL6322 still checks the ...
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MOSFETs. The ΔV BOOT_CAP allowable droop in the rail of the upper gate drive. 1.6 1.4 1.2 1. 0.8 0 100nC GATE 0.4 50nC 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 ΔV BOOT_CAP FIGURE 9. ...
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AMD soft-start sequence. For the Intel VR10 and VR11 modes of operation, the soft-start sequence is composed of four periods, as shown in Figure 11. Once the ISL6322 is released from shutdown and soft-start ...
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OUTPUT PRECHARGED ABOVE DAC LEVEL OUTPUT PRECHARGED BELOW DAC LEVEL GND> GND> FIGURE 13. SOFT-START WAVEFORMS FOR ISL6322-BASED MULTIPHASE CONVERTER Pre-Biased Soft-Start The ISL6322 also has the ability to start up into a pre-charged output, without causing ...
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The LGATE outputs remain high and PWM4 remains low until VDIFF falls 100mV below the OVP threshold that tripped the overvoltage protection circuitry. The ISL6322 will continue to protect the load ...
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OUTPUT CURRENT, 50A/DIV 0A OUTPUT VOLTAGE, 500mV/DIV 0V 3ms/DIV FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE Individual Channel Overcurrent Limiting The ISL6322 has the ability to limit the current in each individual channel without shutting down the entire regulator. This ...
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Acknowledge Each address and data transmission uses 9 clock pulses. The ninth pulse is the acknowledge bit (A). After the start condition, the master sends 7 slave address bits and a R/W bit during the next 8 clock pulses. During ...
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I C Read and Write Protocol Write to a Single Register S slave_addr + W A reg_addr Write to Both Registers S slave_addr + W A 0000_0000 Read from a Single Register S slave_addr + W A reg_addr Read ...
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TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING OFFSET) (Continued) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 X X VO5 VO4 VO3 VO2 ...
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TABLE 9. REGISTER RGS2 (ADAPTIVE DEADTIME CONTROL/OVERVOLTAGE PROTECTION/SWITCHING FREQUENCY) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 X X DT1 DT0 OVP ...
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An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage ...
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PVCC BOOT R G HI1 UGATE R R LO1 G1 PHASE FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC HI2 LGATE LO2 G2 FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH The total gate drive ...
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Plug the inductor L and DCR component values, and the value for C chosen in step 1, into Equation calculate the value for ------------------------- OCP ⋅ 1 DCR C ...
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Load-line Regulation” on page 35 and “Compensation without Load-line Regulation” on page 36. COMPENSATION WITH LOAD-LINE REGULATION The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the ...
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COMP IDROOP VDIFF FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE REGULATION COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with ...
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The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see “Interleaving” on page 11 and Equation 2), a voltage develops across the bulk ...
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0.5 I L, 0.75 I L,PP O L,PP 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER ...
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PHASE terminal to output inductors short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for ...
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IDROOP VDIFF COMP VSEN RGND +5V VCC (CF1) R OFS OFS FS REF REF SCL SDA SS / RST / ISL6322 VID7 VID6 VID5 VID4 ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 41 ...