AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 115
AT89C51CC03U-S3SIM
Manufacturer Part Number
AT89C51CC03U-S3SIM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51CC03U-S3SIM.pdf
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4182I–CAN–06/05
Table 60. CANBT1 Register
CANBT1 (S:B4h)
CAN Bit Timing Registers 1
Note:
No default value after reset.
Number
Bit
6-1
7
-
7
0
The CAN controller bit timing registers must be accessed only if the CAN controller is dis-
abled with the ENA bit of the CANGCON register set to 0.
See Figure 52.
Bit Mnemonic Description
BRP 5
BRP5:0
6
-
-
BRP 4
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud rate prescaler
The period of the CAN controller system clock Tscl is programmable and
determines the individual bit timing.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
BRP 3
4
Tscl =
BRP 2
3
BRP[5..0] + 1
Fcan
BRP 1
2
BRP 0
1
0
-
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