DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet
![no-image](/images/no-image-200.jpg)
DAC1405D750HW
Available stocks
Related parts for DAC1405D750HW
DAC1405D750HW Summary of contents
Page 1
DAC1405D750 Dual 14-bit DAC 750 Msps; 4× and 8× interpolating Rev. 01 — 10 March 2010 1. General description The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4× or 8× interpolating filters optimized ...
Page 2
... Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number Package Name DAC1405D750HW HTQFP100 DAC1405D750_1 Preliminary data sheet Dual 14-bit DAC 750 Msps; 4× and 8× interpolating Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 × 14 × 1 mm; exposed die pad All information provided in this document is subject to legal disclaimers. Rev. 01 — ...
Page 3
SDO 62 DAC1405D750 18 to 25, FIR1 FIR2 28 to 31, 34, 35 LATCH I0 to I14 × 2 × dual port/ interleaved data modes FIR1 FIR2 41, 42, LATCH × 2 ...
Page 4
... Fig 2. Pin configuration DAC1405D750_1 Preliminary data sheet Dual 14-bit DAC 750 Msps; 4× and 8× interpolating DAC1405D750HW AGND All information provided in this document is subject to legal disclaimers. Rev. 01 — 10 March 2010 DAC1405D750 75 V DDA(3V3) 74 AUXBP 73 AUXBN 72 AGND ...
Page 5
NXP Semiconductors 6.2 Pin description Table 2. Symbol V DDA(3V3) AUXAP AUXAN AGND V DDA(1V8) V DDA(1V8) AGND CLKP CLKN AGND V DDA(1V8) SYNCP SYNCN TM1 TM0 V DD(IO)(3V3) GNDIO I13 I12 I11 I10 DDD(1V8) ...
Page 6
NXP Semiconductors Table 2. Symbol V DDD(1V8) Q13/SELIQ Q12 DGND V DDD(1V8) Q11 Q10 Q9 Q8 DGND V DDD(1V8 GNDIO V DD(IO)(3V3) TM3 SDO SDIO SCLK SCS_N RESET_N d.n.c. VIRES GAPOUT V ...
Page 7
NXP Semiconductors Table 2. Symbol V DDA(1V8) AGND V DDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND AGND [ power supply G = ground ...
Page 8
NXP Semiconductors 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage (3.3 V) DD(IO)(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog supply voltage (1.8 ...
Page 9
NXP Semiconductors 9. Characteristics Table 5. Characteristics 1 DDA(1V8) DDD(1V8) DDA(3V3) − ° ° +85 C; typical values measured at T amb otherwise specified. Symbol Parameter V input/output supply ...
Page 10
NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3) − ° ° +85 C; typical values measured at T amb otherwise specified. Symbol Parameter Clock inputs (CLKP and ...
Page 11
NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3) − ° ° +85 C; typical values measured at T amb otherwise specified. Symbol Parameter Input timing (see Figure ...
Page 12
NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3) − ° ° +85 C; typical values measured at T amb otherwise specified. Symbol Parameter IMD3 third-order intermodulation distortion ...
Page 13
NXP Semiconductors 10. Application information 10.1 General description The DAC1405D750 is a dual 14-bit DAC which operates 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. ...
Page 14
NXP Semiconductors RESET_N (optional) SCS_N SCLK SDIO R SDO (optional) R/W indicates the mode access, (see Fig 3. SPI protocol Table 6. R Table 7 Table A4: ...
Page 15
NXP Semiconductors The SPI timing characteristics are given in Table 8. Symbol f SCLK t w(SCLK) t su(SCS_N) t h(SCS_N) t su(SDIO) t h(SDIO) t w(RESET_N) 10.2.3 Detailed descriptions of registers An overview of the details for all registers is ...
Page 16
Table 9. Register allocation map Address Register name R/W Bit definition Dec Hex Bit 7 0 00h COMMon R/W 3W_SPI 1 01h TXCFG R/W NCO_ON 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W 5 05h ...
Page 17
NXP Semiconductors 10.2.4 Detailed register descriptions Please refer to following tables, all the values shown in bold are the default values. Table 10. Default settings are shown highlighted. Bit Table 11. Default ...
Page 18
NXP Semiconductors Table 11. Default settings are shown highlighted. Bit Symbol MODULATION[2: INTERPOLATION[1:0] Table 12. Default settings are shown highlighted. Bit PLL_DIV[1: DAC_CLK_DELAY[1:0] R/W 0 ...
Page 19
NXP Semiconductors Table 14. Bit FREQ_NCO[15:8] Table 15. Bit FREQ_NCO[23:16] Table 16. Bit FREQ_NCO[31:24] Table 17. Bit PH_NCO[7:0] Table 18. Bit PH_NCO[15:8] Table 19. Default ...
Page 20
NXP Semiconductors Table 21. Bit DAC_A_GAIN_ DAC_A_ Table 22. Default settings are shown highlighted. Bit DAC_B_OFFSET[5:0] Table 23. Bit DAC_B_GAIN_ DAC_B_GAIN_ Table 24. ...
Page 21
NXP Semiconductors Table 26. Default settings are shown highlighted. Bit Table 27. Bit AUX_A[9:2] Table 28. Default settings are shown highlighted. Bit AUX_A[1:0] ...
Page 22
NXP Semiconductors 10.2.5 Recommended configuration It is recommended that the following additional settings are used to obtain optimum performance 750 Msps Table 31. Address Dec 10.3 Input data The setting applied to MODE_SEL (register ...
Page 23
NXP Semiconductors Fig 6. In Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch ...
Page 24
NXP Semiconductors 10.4 Input clock The DAC1405D750 can operate at the following clock frequencies: PLL on 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off 750 MHz The input clock ...
Page 25
NXP Semiconductors (SYNCP − SYNCN) Fig 10. Input timing diagram when internal PLL bypassed (off) 10.5.1 Timing when using the internal PLL (PLL on) In Table 33 The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see map”) allows the frequency between ...
Page 26
NXP Semiconductors Table 36. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) 10.7 Quadrature modulator and ...
Page 27
NXP Semiconductors 10.7.1 NCO in 32-bit When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: f NCO ...
Page 28
NXP Semiconductors 10.9 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs The output current depends on the digital input data: I IOUTP I ...
Page 29
NXP Semiconductors Fig 11. Internal reference configuration This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an ...
Page 30
NXP Semiconductors Table 39. Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal The settings applied to DAC_A_GAIN_FINE[5:0] (see (address 0Ah) bit “DAC_B_Cfg_2 register (address 0Dh) bit full-scale current (see Table 40. Default settings are shown highlighted. DAC_GAIN_FINE[5:0] ...
Page 31
NXP Semiconductors Table 41. Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal −2048 −2047 ... − ... +2046 +2047 10.12 Analog output The DAC1405D750 has two output channels each of which produces two complementary current outputs. These allow the ...
Page 32
NXP Semiconductors 10.13 Auxiliary DACs The DAC1405D750 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and ...
Page 33
NXP Semiconductors The DAC1405D750 differential outputs can operate recommended to connect the center tap of the transformer Ω resistor connected to the 3.3 V analog power supply, in order to adjust the ...
Page 34
NXP Semiconductors Fig 16. An example interface to a 3.3 V The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 17 a 1.7 V Fig 17. An ...
Page 35
NXP Semiconductors Fig 18. An example interface to a 3.3 V The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, ...
Page 36
NXP Semiconductors Fig 19. An example interface to a 0.5 V 10.15 Power and grounding In order to obtain optimum performance recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 ...
Page 37
NXP Semiconductors 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad y exposed die pad side pin 1 index 100 ...
Page 38
NXP Semiconductors 12. Abbreviations Table 43. Acronym B CDMA CML CMOS DAC FIR GSM IF IMD3 LISB LMDS LSB LTE LVDS MMDS MSB NCO NMOS PLL SFDR SPI TD-SCDMA UISB WCDMA WiMAX DAC1405D750_1 Preliminary data sheet Dual 14-bit DAC, up ...
Page 39
NXP Semiconductors 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. ...
Page 40
NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
Page 41
NXP Semiconductors In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use ...
Page 42
NXP Semiconductors 17. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...
Page 43
NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...