UDA1343 PHILIPS [NXP Semiconductors], UDA1343 Datasheet - Page 8

• Manufacturer Part Number: UDA1343
• Description: Economy audio CODEC with features
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Decimation filter (ADC)
The decimation from 64f
The first stage realizes a 4th-order
This filter decreases the sample rate by 16. The second
stage consists of 2 half-band filters and a recursive filter,
each decimating by a factor of 2.
Table 2 Digital decimation filter characteristics
In the ADC path there is a volume control with a range of
0 dB to 66 dB and
roll-off soft mute.
Note: it should be noted that the digital output level is
inversely proportional to the ADC analog power supply.
This means that with a constant analog input level and
increasing analog power supply, the digital output level will
decrease proportionally.
Overload detection (ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is larger than
possible digital swing. When this condition is detected the
OVERFL output (pin 9) is forced HIGH for at least 512f
cycles (11.6 ms at f
each infringement.
Interpolation filter (DAC)
The digital filter interpolates from 1 to 128f
cascade of a recursive filter and an FIR filter.
Table 3 Digital interpolation filter characteristics
2000 Jan 12
Pass-band ripple
Stop band
Dynamic range
Overall gain with 0 dB
input to the ADC
Pass-band ripple
Stop band
Dynamic range
Gain
1 dB (the actual figure is 1.16 dB) of the maximum
Economy audio CODEC with features
ITEM
ITEM
s
= 44.1 kHz). This time-out is reset for
dB in 0.25 dB steps, and a cosine
s
CONDITIONS
CONDITIONS
to 1f
0
0
0
0
>0.55f
>0.55f
s
DC
DC
is performed in two stages.
0.45f
0.45f
0.45f
0.45f
s
s
sin x
----------- -
s
s
s
s
x
characteristic.
s
VALUE (dB)
VALUE (dB)
by means of a
116.5
114
0.05
1.16
0.03
3.5
50
65
s
8
Digital silence detector
The UDA1343 is equipped with a digital silence detector
on the digital data input. This detects whether a certain
amount of consecutive samples are 0. The status of the
digital silence detector can be read from the
microcontroller interface.
The number of samples can be set via the L3 interface to
3200, 4800, 9600 or 19600 samples.
Mute
Muting the DAC will result in a cosine roll-off soft mute,
using 32
cosine roll-off curve is illustrated in Fig.3.
Double speed
SInce the device supports a sampling range of
8 to 110 kHz, the device can support double speed (e.g.
for 44.1 kHz and 48 kHz) by just doubling the system
speed. In double speed all features are available.
handbook, halfpage
Fig.3 Mute as a function of raised cosine roll-off.
factor
mute
0.8
0.6
0.4
0.2
1
0
0
4 = 128 samples (at 44.1 kHz this is 3 ms). The
1
Preliminary specification
2
UDA1343TT
t (ms)
MGS755
3