MAXQ7665AATM+ MAXIM [Maxim Integrated Products], MAXQ7665AATM+ Datasheet - Page 25

• Manufacturer Part Number: MAXQ7665AATM+
• Description: 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems
• Manufacturer: MAXIM [Maxim Integrated Products]

Note: The MAXQ7665A–MAXQ7665D do not have sec-
ondary timer I/O pins (such as T0B and T1B) that are
present in some other MAXQ products.
A hardware multiplier supports high-speed multiplica-
tions. The multiplier is capable of completing a 16-bit x
16-bit multiply in a single cycle and contains a 48-bit
accumulator that requires one more cycle. The multipli-
er is not part of the MAXQ core function but a peripher-
al that performs seven different multiply operations
without interfering with the normal core functions:
• Unsigned 16-bit multiplication (one cycle)
• Unsigned 16-bit multiplication and accumulation
• Unsigned 16-bit multiplication and subtraction (two
• Signed 16-bit multiplication (one cycle)
• Signed 16-bit multiplication and negate (one cycle)
• Signed 16-bit multiplication and accumulation (two
• Signed 16-bit multiplication and subtraction (two
Figure 9 illustrates the simplified hardware multiplier cir-
cuitry. Two 16-bit parallel-load registers and a 48-bit
Figure 9. 16-Bit Hardware Multiplier Functional Diagram
(two cycles)
cycles)
cycles)
cycles)
OVERFLOW
16-Bit x 16-Bit Hardware Multiplier
15
MC1R
______________________________________________________________________________________
0
MC0R
15 0
SUS
MMAC
MSUB
OPCS
SQU
CLD
MCW
15
MA
15
MC2
MULTIPLIER
0
0
15
15
MC1
16-Bit RISC Microcontroller-Based
0
MB
15 0
MC0
Smart Data-Acquisition Systems
0
accumulator are used: operand A (MA), operand B
(MB), and accumulator (MC). The accumulator is formed
by three 16-bit parallel registers (MC2, MC1, and MC0).
The overflow bit is organized in the MCNT status/control
register. The multiplicand and the multiplier are initially
loaded into the MA and MB registers, respectively.
Loading the required operands triggers the respective
multiply, multiply-accumulate/subtract or multiply-negate
operation. The multiply operation completes in a single
cycle with the results in the read-only MC1R/MC0R reg-
ister. The multiply-accumulate/subtract operation
requires one extra wait cycle for the results to be stable
in the MC2, MC1, and MC0 registers.
The main arithmetic unit is the 16-bit x 16-bit multiplier,
which processes operands feeding from the MA and
MB registers and generates a 32-bit final product. The
product value goes through the 32-bit adder to perform
final accumulation with zeroes for multiply operation or
with the contents from the MC1 and MC0 registers for
multiply-accumulation. The final sum is accessible
directly from the accumulator.
To support negate operations including signed multiply-
negate and signed and unsigned multiply-subtract, the
operand in MA is negated by 1’s complement operation
before being supplied to the arithmetic unit and the par-
tial product terms are sign corrected. Refer to the
MAXQ7665/MAXQ7666 User’s Guide for more detailed
information.
The MAXQ7665A–MAXQ7665D incorporate a CAN
controller that is fully compliant with the CAN 2.0B
specification.
The µC interface to the CAN controller is broken into
two groups of registers. To simplify the software associ-
ated with the operation of the CAN controllers, most of
the global CAN status and controls as well as the indi-
vidual message center control/status registers are
located in the peripheral register map. The remaining
registers associated with the data identification, identifi-
cation masks, format, and data are located in a dual
port memory to allow the CAN controller and the
processor access to the required functions. The CAN
controller can directly access the dual port memory. A
dedicated interface is incorporated to support dual port
memory accessing by the processor through the CAN
0 data pointer (C0DP) and the CAN 0 data buffer
(C0DB) special function registers.
CAN Interface Bus
25