SI3012 ETC, SI3012 Datasheet - Page 46

• Manufacturer Part Number: SI3012
• Description: 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
• Manufacturer: ETC

S i3 03 5
Pin Descriptions: Si3021
46
SOIC
Pin #
1
2
3
4
5
6
7
8
9
TSSOP
Pin #
13
14
15
16
1
2
3
4
5
FC/RGDT
FSYNC
RESET
MCLK
SCLK
Pin Name
SDO
FC/RGDT
SDI
FSYNC
RESET
V
MCLK
AOUT
SCLK
D
SDO
SDI
V
D
Si3021 (SOIC)
1
2
3
4
5
6
7
8
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal
clock or modem/DSP.
Frame Sync Output.
Data framing signal that is used to indicate the start and stop of a
communication/data frame.
Serial Port Bit Clock Output.
Controls the serial data on SDO and latches the data on SDI.
Digital Supply Voltage.
Provides the digital supply voltage to the Si3021, nominally either 5 V or
3.3 V.
Serial Port Data Output.
Serial communication data that is provided by the Si3021 to the modem/DSP.
Serial Port Data Input.
Serial communication and control data that is generated by the modem/DSP
and presented as an input to the Si3021.
Secondary Transfer Request Input/Ring Detect Output.
An optional signal to instruct the Si3021 that control data is being requested
in a secondary frame. When daisy chain is enabled, this pin becomes the
ring detect output. Produces an active low rectified version of the ring signal.
Reset Input.
An active low input that is used to reset all control registers to a defined, ini-
tialized state. Also used to bring the Si3034 out of sleep mode.
Analog Speaker Output.
Provides an analog output signal for driving a call progress speaker.
Table 21. Si3021 Pin Descriptions
16
15
14
13
12
10
11
9
OFHK
RGDT/FSD
M0
V
GND
C1A
M1
AOUT
A
Rev. 1.2
FC/RGDT
RESET
AOUT
GND
SDO
C1A
SDI
M1
Description
Si3021 (TSSOP)
1
2
3
4
5
6
7
8
16
15
14
13
12
10
11
9
V
SCLK
FSYNC
MCLK
OFHK
RGDT/FSD
M0
V
A
D