SI3012 ETC, SI3012 Datasheet - Page 23

• Manufacturer Part Number: SI3012
• Description: 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
• Manufacturer: ETC

The main design consideration is the generation of a
base frequency, defined as the following:
N1 (Register 7) and M1 (Register 8) are 8-bit unsigned
values. F
Table 18 lists several standard crystal oscillator rates
that could be supplied to MCLK. This list simply
represents a sample of MCLK frequency choices. Many
more are possible.
After the first PLL has been setup, the second PLL can
be programmed easily. The values for N2 and M2
(Register 9) are shown in Table 17. N2 and M2 are 4-bit
unsigned values.
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N1 (Register 7) must always be written first,
immediately followed by a write to M1 (Register 8). For
PLL2, the CGM bit must be set as desired prior to
writing N2/M2 (Register 9). Changes to the CGM bit
only take effect when N2/M2 are written.
Note: The values shown in Table 17 and Table 18 satisfy the
F Base
F Base
Table 17. N2, M2 Values (CGM = 0, 1)
equations above. However, when programming the
registers for N1, M1, N2, and M2, the value placed in
these registers must be one less than the value calcu-
lated from the equations. For example, for CGM = 0
with a MCLK of 48.0 MHz, the values placed in the N1
and M1 registers would be 0x7C and 0x5F, respec-
tively. If CGM = 1, a non-zero value must be pro-
grammed to Register 9 in order for the 16/25 ratio to
take effect.
MCLK
=
=
F
--------------------------------------------- -
Fs (Hz)
MCLK
10286
F
----------------------------------
7200
8000
8229
8400
9000
9600
is the clock provided to the MCLK pin.
MCLK
N1 25
N1
M1 16
M1
=
N2
2
9
7
6
4
3
7
=
36.864MHz CGM
36.864MHz CGM
M2
10
10
2
8
7
5
4
,
,
=
=
0
1
Rev. 1.2
PLL Lock Times
The Si3035 changes sample rates very quickly.
However, lock time will vary based on the programming
of the clock generator. The major factor contributing to
PLL lock time is the CGM bit. When the CGM bit is used
(set to 1), PLL2 will lock slower than when CGM is 0.
The following relationships describe the boundaries on
PLL locking time:
For modem designs, it is recommended that PLL1 be
programmed
programming of PLL1 is necessary. The CGM bit and
PLL2 can be programmed for the desired initial sample
PLL1 lock time < 1 ms (CGM = 0,1)
PLL2 lock time: 100 us to 1 ms (CGM = 0)
PLL2 lock time <1 ms (CGM = 1)
MCLK (MHz)
10.0000
10.3680
14.7456
16.0000
18.4320
24.5760
25.8048
33.8688
44.2368
46.0800
47.9232
48.0000
56.0000
60.0000
11.0592
1.8432
4.0000
4.0960
5.0688
6.0000
6.1440
8.1920
9.2160
12.288
Table 18. MCLK Examples
during
147
125
N1
11
32
25
32
96
13
35
25
1
5
1
5
1
1
9
3
1
2
5
1
7
5
initialization.
225
144
160
125
M1
20
72
80
48
32
10
18
75
10
10
96
36
24
9
6
4
3
5
2
4
Si3035
No
CGM
0
1
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
further
23