LTC3547 LINER [Linear Technology], LTC3547 Datasheet - Page 12

• Manufacturer Part Number: LTC3547
• Description: Dual Monolithic 300mA Synchronous Step-Down Regulator
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC3547
Thermal Considerations
In a majority of applications, the LTC3547 does not dis-
sipate much heat due to its high effi ciency. In the unlikely
event that the junction temperature somehow reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
The goal of the following thermal analysis is to determine
whether the power dissipated causes enough temperature
rise to exceed the maximum junction temperature (125°C)
of the part. The temperature rise is given by:
Where P
θ
to the ambient temperature.
The junction temperature, T
As a worst-case example, consider the case when the
LTC3547 is in dropout on both channels at an input volt-
age of 2.7V with a load current of 300mA and an ambi-
ent temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the R
of the main switch is 0.9Ω. Therefore, power dissipated
by each channel is:
Given that the thermal resistance of a properly soldered
DFN package is approximately 76°C/W, the junction
temperature of an LTC3547 device operating in a 70°C
ambient temperature is approximately:
which is well below the absolute maximum junction tem-
perature of 125°C.
12
JA
T
T
P
T
RISE
is the thermal resistance from the junction of the die
J
J
D
= T
= (2 • 0.081W • 76°C/W) + 70°C = 82.3°C
= I
= P
OUT 2
RISE
D
is the power dissipated by the regulator and
D
+ T
• θ
• R
AMBIENT
JA
DS(ON)
U
= 81mV
U
J
, is given by:
W
U
DS(ON)
(7)
(6)
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3547. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
1. Does the capacitor C
2. Are the respective C
3. The resistor divider, R1 and R2, must be connected
4. Keep sensitive components away from the SW pins if
5. A ground plane is preferred, but if not available, keep
6. Flood all unused areas on all layers with copper. Flood-
and GND (Pin 5) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
The (–) plate of C
(–) plate of C
between the (+) plate of C
line terminated near GND (Pin 5). The feedback sig-
nals V
components and traces, such as the SW lines (Pins 4
and 6), and their trace length should be minimized.
possible. The input capacitor C
R2, R3 and R4 should be routed away from the SW
traces and the inductors.
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
current path of C
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to V
FB1
and V
IN
.
IN
FB2
IN
or GND.
OUT
should be routed away from noisy
or C
IN
OUT
returns current to GND and the
connect to the power V
OUT
and L closely connected?
.
OUT1
IN
and a ground sense
and the resistors R1,
IN
(Pin 3)
3547fa