LTC3547 LINER [Linear Technology], LTC3547 Datasheet - Page 11

• Manufacturer Part Number: LTC3547
• Description: Dual Monolithic 300mA Synchronous Step-Down Regulator
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
LTC3547 circuits: 1) V
losses, 3) I
1) The V
2) The switching current is the sum of the MOSFET driver
% Effi ciency = 100% – (L1 + L2 + L3 + ...)
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V
of V
rent. In continuous mode, I
Q
Electrical Characteristics which excludes MOSFET
driver and control currents. V
small (<0.1%) loss that increases with V
no load.
T
and Q
IN
IN
that is typically much larger than the DC bias cur-
IN
2
current is the DC supply current given in the
to ground. The resulting dQ/dt is a current out
B
R losses, 4) other system losses.
are the gate charges of the internal top and
U
IN
quiescent current, 2) switching
U
GATECHG
IN
W
current results in a
= f
O
(Q
T
+ Q
IN
U
, even at
B
), where
3) I
4) Other “hidden” losses, such as copper trace and in-
bottom MOSFET switches. The gate charge losses are
proportional to V
pronounced at higher supply voltages.
The R
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I
ternal battery resistances, can account for additional
effi ciency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure that
C
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
the internal switches, R
R
fl ows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
(DC) as follows:
2
IN
R losses are calculated from the DC resistances of
R
L
I
2
. In continuous mode, the average output current
SW
R losses = I
has adequate charge storage and very low ESR at
DS(ON)
= (R
DS(ON)TOP
for both the top and bottom MOSFETs can
OUT 2
IN
and thus their effects will be more
) • (DC) + (R
• (R
SW
SW
DS(ON)
+ R
, and external inductor,
2
R losses:
L
DS(ON)BOT
)
and the duty cycle
LTC3547
) • (1– DC)
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