P51XAG30KFA PHILIPS [NXP Semiconductors], P51XAG30KFA Datasheet - Page 12

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P51XAG30KFA

Manufacturer Part Number
P51XAG30KFA
Description
XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
Philips Semiconductors
timer register is loaded with FFFF hex. The underflow also sets the
TF2 flag, which can generate an interrupt if enabled.
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution, if
needed. the EXF2 flag does not generate an interrupt in this mode.
As the baud rate generator, timer T2 is incremented by TCLK.
Baud Rate Generator Mode
By setting the TCLKn and/or RCLKn in T2CON or T2MOD, the
Timer 2 can be chosen as the baud rate generator for either or both
UARTs. The baud rates for transmit and receive can be
simultaneously different.
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.6.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed (1) to input the external clock for
Table 1. Timer 2 Operating Modes
1999 Apr 07
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
TSTAT
Bit Addressable
Reset Value: 00H
T2MOD
Bit Addressable
Reset Value: 00H
TR2
0
1
1
1
1
BIT
TSTAT.2
TSTAT.0
BIT
T2MOD.5 RCLK1
T2MOD.4 TCLK1
T2MOD.1 T2OE
T2MOD.0 DCEN
Address:411
Address:419
CP/RL2
SYMBOL FUNCTION
SYMBOL
T1OE
T0OE
X
0
0
1
X
Receive Clock Flag.
Transmit Clock Flag. RCLK1 and TCLK1 are used to select Timer 2 overflow rate as a clock source
for UART1 instead of Timer T1.
When 0, this bit allows the T2 pin to clock Timer 2 when in the counter mode.
When 1, T2 acts as an output and toggles at every Timer 2 overflow.
Controls count direction for Timer 2 in autoreload mode.
DCEN=0 counter set to count up only
DCEN=1 counter set to count up or down, depending on T2EX (see text).
RCLK+TCLK
FUNCTION
When 0, this bit allows the T1 pin to clock Timer 1 when in the counter mode.
When 1, T1 acts as an output and toggles at every Timer 1 overflow.
When 0, this bit allows the T0 pin to clock Timer 0 when in the counter mode.
When 1, T0 acts as an output and toggles at every Timer 0 overflow.
X
0
0
0
1
MSB
MSB
Figure 5. Timer 0 And 1 Extended Status (TSTAT)
Figure 6. Timer 2 Mode Control (T2MOD)
DCEN
X
X
X
0
1
RCLK1
12
TCLK1
16-bit auto-reload, counting up or down depending on T2EX pin
Timer/Counter 2 or (2) to output a 50% duty cycle clock ranging from
3.58Hz to 3.75MHz at a 30MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (TCAP2H, TCAP2L) as
shown in this equation:
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate will be
1/8 of the Clock-Out frequency.
2
(65536 * TCAP2H, TCAP2L)
16-bit auto-reload, counting up
T1OE
Baud rate generator
Timer off (stopped)
16-bit capture
TCLK
MODE
T2OE
DCEN
T0OE
SU00612B
LSB
LSB
Product specification
SU00610B
XA-G3

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