AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 30

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

AD5522
REGISTER SELECTION
The serial word assignment consists of 29 bits. Bits 28 through
to 22 are common to all registers, whether writing to or reading
from the device. PMU3 to PMU0 data bits address each PMU
channel (or associated DAC register). When PMU3 to PMU0
are all zeros, the System Control Register is addressed. Mode
Bits MODE0 and MODE1 address the different sets of DAC
registers and the PMU register.
Readback Control, RD/ WR
The R/ W bit set high initiates a readback sequence of PMU,
Alarm, Comparator, System Control Register or DAC
information as determined by address bits.
Table 14. Read and Write Functions of the AD5522
B28
RD/ WR
WRITE FUNCTIONS
0
0
0
0
0
WRITE ADDRESSED DAC OR PMU REGISTER
0
0
0
0
0
0
0
0
0
READ FUNCTIONS
1
1
1
1
READ ADDRESSED DAC or PMU REGISTER – Can only read one PMU or DAC register at one time.
1
1
1
1
NOP (No Operation)
If a NOP (No Operation) command is loaded, no change is made to DAC or PMU registers. This code is useful when performing a read
back of a register within the device (via the SDO pin) where a change of DAC code or PMU function may not be required
Reserved Commands
Any bit combination that is not described in the Register address tables for the PMU, DAC and System Control Registers are Reserved
commands. These commands are unassigned commands; they are reserved for factory use. To ensure correct operation of the device, do
not used reserved commands.
B27
PMU3
0
0
0
0
0
0
0
0
0
-
1
-
1
1
0
0
0
0
0
0
0
1
B26
PMU2
0
0
0
0
0
0
0
0
1
-
0
-
1
1
0
0
0
0
0
0
1
0
B25
PMU1
0
0
0
0
0
0
1
1
0
-
0
-
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
-
-
0
1
0
0
0
B24
PMU0
1
0
1
0
0
0
0
1
0
0
B23
MODE1
0
0
1
1
1
Select DAC or PMU Registers.
See Table 13
0
0
1
1
PMU/DAC REGISTER ADDRESS
SEE
Table 13
B22
MODE0
0
1
0
1
1
0
1
0
1
Rev. PrM | Page 30 of 48
B21 to B0
DATA BITS
DATA BITS
DATA BITS
DATA BITS
11 1111 1111 1111 1111 1111b
DATA BITS other than all 1’s
DATA BITS
All zeros
All zeros
X
All zeros
DAC ADDRESS SEE
Table 21
PMU Address Bits, PMU3, PMU2, PMU1, PMU0
Bits PMU3 through PMU0 address each of the PMU channels
on chip. This allows individual control of each PMU channel or
any manner of combined addressing in addition to multi
channel programming. PMU bits also allow access to write
registers such as the System Control Register and the many
DAC registers, in addition to reading from all the registers.
Table 13. Mode Bits
B23
MODE1
0
0
1
1
B22
MODE0
0
1
0
1
SELECTED REGISTER
CH3
Write to System Control Register (
RESERVED
RESERVED
NOP (No Operation)
RESERVED
×
×
×
×
-
CH3
-
CH3
CH3
Read from System Control Register
Read from Comparator Status Registers
Reserved
Read from Alarm Status Register
×
×
×
CH3
WRITE FUNCTION
Action
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x1)
Preliminary Technical Data
CH2
×
×
×
CH2
-
×
-
CH2
CH2
×
×
CH2
×
CH1
×
CH1
CH1
×
-
×
-
CH1
CH1
×
CH1
×
×
Table 16
CH0
CHO
×
CH0
×
-
×
-
×
CH0
CH0
×
×
×
)