h8s-2138 Renesas Electronics Corporation., h8s-2138 Datasheet - Page 963
h8s-2138
Manufacturer Part Number
h8s-2138
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2138.pdf
(1061 pages)
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LPWRCR—Low-Power Control Register
Bit
Initial value
Read/Write
Direct-transfer on flag
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
0
1
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
• When a SLEEP instruction is executed in subactive mode, a transition is made to
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
• When a SLEEP instruction is executed in subactive mode, a transition is made directly
a transition is made to sleep mode, software standby mode, or watch mode*
subsleep mode or watch mode
a transition is made directly to subactive mode * , or a transition is made to sleep mode
or software standby mode
to high-speed mode, or a transition is made to subsleep mode
be set.
DTON
R/W
7
0
Note: * When a transition is made to watch mode or subactive mode,
Low-speed on flag
0
1
• When a SLEEP instruction is executed in high-speed mode or
• When a SLEEP instruction is executed in subactive mode, a transition
• After watch mode is cleared, a transition is made to high-speed mode
• When a SLEEP instruction is executed in high-speed mode a
• When a SLEEP instruction is executed in subactive mode, a transition
• After watch mode is cleared, a transition is made to subactive mode
medium-speed mode, a transition is made to sleep mode, software
standby mode, or watch mode *
is made to watch mode, or directly to high-speed mode
transition is made to watch mode or subactive mode *
is made to subsleep mode or watch mode
LSON
R/W
high-speed mode must be set.
6
0
NESEL
R/W
Noise elimination sampling frequency select
0
1
5
0
Sampling at
Sampling at
EXCLE
R/W
Subclock input enable
4
0
0
1
Subclock input from EXCL pin is disabled
Subclock input from EXCL pin is enabled
Rev. 4.00 Jun 06, 2006 page 909 of 1004
divided by 32
divided by 4
H'FF85
—
—
3
0
Appendix B Internal I/O Registers
—
—
2
0
—
—
1
0
REJ09B0301-0400
—
—
0
0
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