cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 41
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cx25870
Manufacturer Part Number
cx25870
Description
Video Encoder With Adaptive Flicker Filtering And Hdtv Output
Manufacturer
Conexant Systems, Inc.
Datasheet
1.CX25870.pdf
(291 pages)
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-12. Slave Interface with a BLANK* Input to the CX25870/871
100381B
SLAVE
BLANK* SIGNAL
transmitted to
the CX25870/871
and received as
an input.
Interfaced Used
of 0xBA) ORed
with Slave Pin
SLAVER (Bit 5
1
NOTE:
• SLAVER bit = 1 the CX25870/871 is the video timing slave. It expects to
• EN_BLANKO is high (=1), signifying the CX25870/871's BLANK* port
• EN_DOT = 0 telling the CX25870/871 to use its internal counters to
• EN_OUT = 0: This ensures the clock output port (CLKO) is three-stated
• After an autoconfiguration command, the CX25870/871 expects active
• In addition to
• SLAVER bit = 1 so the CX25870/871 is the video timing slave. It will
• EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port
• EN_DOT = 1, telling the CX25870/871 to use the BLANK* signal it is
• EN_OUT = 0: This will ensure the clock output port (CLKO) is
receive the syncs from the graphics controller. Since the CX25870 is in
slave mode, the HSYNC* and VSYNC* outputs will be three-stated and
the CX25870/871 will be set up to receive these timing signals from the
graphics controller.
is an output or that NO BLANK* signal is used as part of the system.
determine the active versus the blanking regions.
from the encoder.
low VSYNC* and HSYNC* signals from the controller. The format of
pixels at input of encoder needs to be 24-bit RGB multiplexed unless
modifications are made to the IN_MODE[3:0] 4-bit sequence.
this interface. The most significant bit of CX25870/871 register 0xA0
must be set. This guarantees that EN_XCLK will be high (=1) which will
allow the CX25870/871 to accept CLKI as the pixel clock source.
expect to receive the syncs from the graphics controller. Since the
CX25870 is in slave mode, then the HSYNC* and VSYNC* outputs will
be three-stated and the CX25870/871 will be set up to receive these timing
signals from the graphics controller.
is an input.
receiving to determine where active video starts (rising edge of BLANK*)
and the HACTIVE register to denote where the blanking region starts.
three-stated from the encoder.
Autoconfiguration Mode #28 and #29 for NTSC and PAL DVD Playback
place the encoder into slave interface where it expects a BLANK* input
(Table
Register 0xC6)
EN_BLANKO
(MSb of
1-11).
0
Conexant
Table
1-11, another bit must be programmed manually with
EN_DOT (Bit 6
of Register
0xC6)
1
EN_OUT (LSb of
Register 0xC4)
0
1.0 Functional Description
1.3 Device Description
EN_XCLK (MSb
of Register
0xA0)
1
1-25
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