cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 112

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

2.0 Internal Registers
2.4 Reading Registers
2.4 Reading Registers
Following a start condition, writing 0x89 and then the desired subaddress initiates the read-back sequence. The
next eight bits of information, returned by the CX25870/871, can be read from the SID pin, most significant bit
first. Alternative address 0x8B is required if the ALTADDR pin is high. Registers 0x00 through 0x06 are read
only. All other registers can be read from or written to.
(VERSION[4:0]) indicate the version number of that particular encoder.
0x06 and 0x02 for legacy purposes) should be read accordingly after writing to CHECK_STAT. For a
description of this process follow the guidelines contained in the
vertical blanking interval, set the AUTO_CHK bit.
S_ACK
M_ACK
NACK
START
STOP
D_ADDR
readdata, it will expect the read transaction to continue.
register reads can be provided with less software overhead.
data transaction occurs.
2-6
The ID[2:0] bits of register 0x00 indicate the part type (CX25870/871 or Bt868/869). The lower five bits
For software detection of a connected TV monitor on each DAC output, the MONSTAT_x bits (found in
To check the status of the monitor connections at the DAC output automatically once per frame during the
The following pseudocode sample should be used for properly reading registers within the CX25870/871.
First, there are some basic action assignments:
Perform the following transaction with the serial master:
Finally, read the data starting at the read_address previously issued:
where:
As long as the CX25870/871 detects an acknowledge from the serial master (M_ACK) after providing the
When no acknowledge is received, the encoder will end the read operation. Using this approach, consecutive
To read just one register location, every programming step remains the same up to the point where the read
• Next, load 46 hex into register 6C. This will write the EN_REG_RD bit to 1. This enables the serial
• Next, use the serial master to write the register address from which read-back will occur:
master to read back all encoder registers.
The slave device generates the acknowledge (i.e., the CX25870/871)
The serial master generates the acknowledge.
No acknowledge is generated by either device.
Serial start condition; falling edge of SID occurs when SIC is high.
Serial stop condition; rising edge of SID occurs when SIC is high.
The device address is 88 hex with ALTADDR = 0, 8A when it is a 1.
– START/D_ADDR/S_ACK/6C/S_ACK/46/S_ACK/STOP
– START/D_ADDR/S_ACK/<read_address>/S_ACK/STOP
– START/D_ADDR+1/S_ACK/<readdata(0)>/M_ACK/<readdata(1)>/M_
readdata(0) is the data from CX25870/871 register <read_address>
readdata(1) is the data from CX25870/871 register <read_address>+1
readdata(2) is the data from CX25870/871 register <read_address>+2
ACK/
<readdata(2)>/M_ACK/.../.../<readdata(n-1)>/M_ACK/<readdata(n)>/
NACK/STOP
Conexant
Flicker-Free Video Encoder with Ultrascale Technology
Section
1.3.46.
CX25870/871
100381B