74HCT132D,652 NXP Semiconductors, 74HCT132D,652 Datasheet - Page 14
![IC QUAD 2IN NAND SCHMITT 14-SOIC](/photos/6/57/65749/14-soic-sot108-1_sml.jpg)
74HCT132D,652
Manufacturer Part Number
74HCT132D,652
Description
IC QUAD 2IN NAND SCHMITT 14-SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HC132N652.pdf
(8 pages)
Specifications of 74HCT132D,652
Number Of Circuits
4
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
NAND Gate - Schmitt Trigger
Number Of Inputs
2
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
NAND
Logic Family
74HCT
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Propagation Delay Time
17 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Logical Function
NAND
Number Of Elements
4
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 125C
Package Type
SO
Number Of Outputs
1
Technology
CMOS
Mounting
Surface Mount
Pin Count
14
Operating Temperature Classification
Automotive
Quiescent Current
2uA
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2774-5
933714140652
933714140652
Philips Semiconductors
AC waveforms 74HCT (continued)
Test circuit for 74HCT
March 1988
handbook, full pagewidth
handbook, full pagewidth
HCMOS family characteristics
Switch position
Note
1. For open-drain N-channel outputs t
TEST
t
t
t
t
C
R
PZH
PZL
PHZ
PLZ
L
T
=
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
SWITCH
GND
V
GND
V
CC
CC
LOW-to-OFF
OFF-to-LOW
HIGH-to-OFF
OFF-to-HIGH
MGK566
OUTPUT
OUTPUT
OUTPUT
ENABLE
GENERATOR
PULSE
Fig.11 Propagation delays of 3-state outputs.
90%
Fig.12 Test circuit for 3-state outputs.
PLZ
t f
1.3 V
10%
and t
V I
t PLZ
enabled
outputs
t PHZ
PZL
R T
are applicable.
10%
D.U.T
V CC
90%
14
o
of
disabled
outputs
V O
C L
t r
t PZL
t PZH
R L = 1 k
50 pF
FAMILY SPECIFICATIONS
1.3 V
MGK563
1.3 V
outputs
enabled
V CC