74HC4049D,653 NXP Semiconductors, 74HC4049D,653 Datasheet

IC HEX INV LEVEL SHIFTER 16SOIC

74HC4049D,653

Manufacturer Part Number
74HC4049D,653
Description
IC HEX INV LEVEL SHIFTER 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC4049D,653

Logic Type
Inverter
Number Of Inputs
1
Number Of Circuits
6
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
2 V ~ 6 V
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Logic Family
HC
Number Of Channels Per Chip
6
Polarity
Inverting
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
6 / 6
Propagation Delay Time
85 ns at 2 V, 17 ns at 4.5 V, 14 ns at 6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
 Details
Other names
74HC4049D-T
74HC4049D-T
933714800653
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number Package
74HC4049N
74HC4049D
74HC4049DB 40 C to +125 C
74HC4049PW 40 C to +125 C
Ordering information
Temperature range
40 C to +125 C
40 C to +125 C
The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the 4049
of the 4000B series. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4049 provides six inverting buffers with a modified input protection structure,
which has no diode connected to V
This feature enables the inverting buffers to be used as logic level translators, which will
convert high level logic to low level logic, while operating from a low voltage power supply.
For example 15 V logic (4000B series) can be converted down to 2 V logic.
The actual input switch level remains related to V
characteristics. At the same time each part can be used as a simple inverter without level
translation.
74HC4049
Hex inverting HIGH-to-LOW level shifter
Rev. 3 — 30 December 2010
Low-power dissipation
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
CC
. Input voltages of up to 15 V may therefore be used.
CC
as mentioned in the static
Product data sheet
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1

Related parts for 74HC4049D,653

74HC4049D,653 Summary of contents

Page 1

Hex inverting HIGH-to-LOW level shifter Rev. 3 — 30 December 2010 1. General description The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the 4049 of the 4000B series specified in compliance with ...

Page 2

... NXP Semiconductors 4. Functional diagram 001aai331 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74HC4049 GND 8 001aan372 Fig 4. Pin configuration DIP16 and SO16 74HC4049 Product data sheet V1/V2 3 V1/V2 5 V1/V2 7 V1/V2 9 V1/V2 11 V1/V2 14 001aan374 Fig 2. IEC logic symbol Fig 5. All information provided in this document is subject to legal disclaimers. ...

Page 3

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 10, 12 11, 14 GND 8 n.c. 13 Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors Fig 6. Input protection for the 74HC4049 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9 ...

Page 5

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 20    4.0 mA 5.2 mA input leakage current supply current GND 6 input I capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C ...

Page 6

... NXP Semiconductors N = number of inputs switching; (C  V  sum of outputs 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. The input (nA) to output (nY) propagation delays Table 8. Measurement points Type 74HC4049 74HC4049 ...

Page 7

... NXP Semiconductors Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC4049 ...

Page 8

... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 9

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 11. Package outline SOT338-1 (SSOP16) ...

Page 11

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC4049PW (TSSOP16 package). Product specification All information provided in this document is subject to legal disclaimers. Rev. 3 — ...

Page 13

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 14

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC4049 Product data sheet 15 ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations ...

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