PLL701-13 PhaseLink (PLL), PLL701-13 Datasheet - Page 4

• Manufacturer Part Number: PLL701-13
• Description: , 1x, 2x, or 4x Out, 24 - 120MHz in = Out, SST
• Manufacturer: PhaseLink (PLL)

3. TIMING CHARACTERISTICS
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and modulation rates
The PLL701-13 provides selectable spread spectrum modulation, as well as selectable modulation rate. Selection
is made by connecting specific pins to a logical “zero” or “one”, according to the output clock selection table and
modulation rate selection table on page 1.
Pins 2 (S2), 3 (S1), 4 (S0), and 7 (S3) are used as inputs to select the spread spectrum modulation as shown on
the output clock selection table (page 1).
Default values for S(0:3) through internal pull-up and pull-down resistor
Selection pins S0 and S3 have an internal pull-down resistor of 30k , pins 2 and 3 (S1 and S2) have an internal
pull-up resistor of 30k . This internal pull-up (or pull-down) resistor will pull the input value to a logical “one” (or
“zero” respectively) by default, i.e. when no resistive load is connected between the pin and GND (VDD
respectively). In order to override the internal pull-up (pull-down), the pin has to be connected to GND (VDD
respectively).
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Input to Output Delay
Cycle to Cycle Jitter
Output Duty Cycle
PARAMETERS
Rise Time
Fall Time
SYMBOL
T
cyc-cyc
D
T
T
T
r
f
Measured at 0.8V ~ 2.0V @ 3.3V
Measured at 2.0V ~ 0.8V @ 3.3V
Over output frequency range @ 3.3V
Low EMI Spread Spectrum Multiplier Clock
CONDITIONS
MIN.
0.78
0.8
45
2
TYP.
0.95
0.85
PLL701-13
50
Rev 11/07/02 Page 4
MAX.
100
1.1
0.9
55
4
UNITS
ns
ns
ns
ps
%